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Intel Atom SoC Architecture
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Let MindShare Bring "Intel® AtomTM SoC Processors" to Life for You

The Atom processor is Intel's low-power embedded processor, targeting the embedded, smart phone, and ultra-mobile PC markets. Atom implements the IA-32 and Intel 64 instruction set, including virtualization support, which has a rich legacy. The Intel 8088 processor was used in the original IBM PC in the 1980s. As time has progressed, Intel has added new hardware and software features to each new generation. The 80386 processor is normally regarded as the baseline for the IA32 instruction set. However, as software compatibility with the original IBM PC and the 8088 is necessary, this class also covers the key parts of the original IBM PC architecture (such as memory map). This class examines the evolution of the platform to assist in understanding the reasons for the architectural features. The class also covers interfacing to other system components (the interconnects) and an overview of the key role that they play in supporting the Intel Atom SoC processor.

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All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.


Comprehensive Intel Atom Processor Course Info

You Will Learn:

  • How the Atom processor works
  • How the platform components function together and divide responsibilities
  • The role and rational for various on-chip interconnects
  • Power management and thermal management features of the processor
  • Atom internal microarchitecture, including pipeline and caches (Bonnell
  •     and Saltwell)
  • Processor modes
  • Instruction set and registers
  • Vector features
  • Interrupt handling
  • Software compatibility and optimization
  • Rational behind the architectural features

Course Length: 4 days

Who Should Attend?

This course is hardware-oriented. It is however suitable for both hardware and firmware/software engineers. The course is ideal for system board-level design engineers who need a broad understanding of the processor or PC architecture. The course is suitable for engineers who need a broad understanding of IA32 architecture.

Course Outline:

  • Patform overview
    • IA32 introduction and history
    • Platform block diagrams, discussing the evolution from legacy PC architecture to modern SoC interconnects
    • Responsibilities of each unit
  • Processor section
    • Modes
      • Real, protected, paged, SMM, big-real
      • Switching modes, and platform bootup
      • Reasons for choosing a mode, BIOS uses of the modes
      • Architectural history
      • 64-bit extensions (not in all models)
    • Registers
    • Memory accesses and the memory map
      • 1 Mbyte legacy region
      • 32-bit restrictions
      • Addressing beyond the 32-bit limits
    • Instruction set
      • Instruction format, and the differences in different modes
      • Arithmetic operations (scalar)
      • SIMD (vector - SSE)
      • Branch operations, near and far transfers
      • Processor control (control registers, MSRs)
      • IO and MMIO and memory, endianness
      • Debug
      • Performance monitoring
      • CPUID and feature detection
    • Segmentation
      • Problems solved by segmentation
      • Real mode segmentation
      • Protected mode segmentation
      • Usage models for segmentation
      • Flat model
      • Deviations from the flat model
    • Task switching
      • Definition of a task, windows and linux differences
      • Hardware features overview
      • Software task switching
    • Paging
      • Introduction to paging, why it is needed
      • Two and three level page tables
      • Execute disable (XD)
      • Why operating systems use the different modes
      • TLB (translation lookaside buffer)
      • TLB behavior under task switching, global pages
    • Hyperthreading
    • Multi-core
    • Caches and TLBs
      • Hardware implementation
      • Coherency across cores, the role of the interconnect
      • Software view
      • Bootup before the memory controller is enabled
    • Execution pipeline
      • Bonnell and Saltwell cores
      • In order execution
      • Macro fusion
      • 2 wide pipeline
    • Functionality not supported (compared with Penryn)  64-bit, VT (model specific)
    • x86 legacy
      • Memory map
      • a20 mask
      • Self modifying code and just-in-time compilers
    • Interrupts, PIC and APIC (local and IO APICs)
    • Software optimization
    • Virtualization Technology (VT) overview (not in all models)
      • Virtualization introduction
      • VT processor assists
      • Uses of VT in the embedded space and mobile spaces
  • On chip interconnects
    • Rational and role of the different interconnects
    • Memory fabric and the role in cache coherency
    • Overview of IOSF (Intel On-chip System Fabric)
    • Overview of OCP
  • Platform overview section
    •   Legacy IO components
    •   PCIe overview
    •   PCI configuration setup
    •   DRAM overview
    •   Bootup sequence, BIOS responsibilities
    •   BIOS configuration
    •   ACPI
      • Static tables
      • Dynamic methods
      • BIOS and SMM
      • Operating system implementations and debug
  • Power management section
    • Frequency changes
    • Sleep states, traditional C states plus C4, C4E, C6
    • Thermal monitoring
    • L2 cache management and power down
    • On chip storage for cache power down

Recommended Prerequisites: Basic understanding of computer architecture

Supplied Materials:

MindShare’s x86 Instruction Set Architecture Book or eBook.
Author: Tom Shanley
Publisher: MindShare Press
Available through the MindShare Store and major bookstore outlets.

Students will be provided with an electronic version of the slides used in class.

 




Hillsboro, OR: 7/8/2014
Folsom, CA: 6/23/2014

x86 Instruction Set Architecture