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Intel Core 2 Processor (Penryn)
Training
Books
eLearning
 

Training


Let MindShare Bring Intel® CoreTM 2 Processors to Life for You

The 80386 processor was the progenitor of the entire IA32 (32-bit Intel Architecture) processor product line. As time has progressed, Intel has added new hardware and software features to the IA32 processor family with each new generation. Starting with the Pentium Pro processor, all Intel IA32 processors (including Celerons and Xeons) up to and including the Pentium III processor were based on the P6 processor core. The Pentium 4 processor was based on the NetBurst core architecture, while the Pentium M, Core Solo and Core Duo processors are variants on the Pentium III processor core. In mid-2006, Intel introduced processors based on the new Core 2 (Penryn) microarchitecture, an enhanced version of the Pentium M processor core. To date, all processors introduced since the Pentium Pro use a variation on the Front Side Bus (FSB) protocol introduced in the Pentium Pro processor. The processor is interfaced to the remainder of the system board components via the chipset. Like Intel’s processors, the chipset’s role has also evolved over time.

MindShare Courses On Intel Core 2 (Penryn):

Course Name
Classroom

Virtual Classroom

eLearning
Comprehensive Intel Core 2 Processor (Penryn)
  4 days

  5 days
 
Intel Core 2 Processor and Chipset Combo Course
5 days
   
Comprehensive x86 APIC Architecture Course
1 day

1 day
Notify Me When Available
Comprehensive Intel 32/64-bit x86 Architecture
3 days

4 days
Notify Me When Available

All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.


Comprehensive Intel Core 2 Processor (Penryn) Course Info

You Will Learn:

  • How the Core 2 processor works
  • Detailed Front Side Bus (FSB) architecture that will give you the understanding of how to design and debug an FSB on the motherboard
  • Power management and thermal management features of the processor
  • Core 2 microarchitecture and Core 2 processor performance enhancement features
  • Intel 64 and IA32 register set and instruction set architecture
  • MMX and SSE features

Course Length: 4 days

Course Outline:

  • Overview of the Processor’s Role
  • Overview of the Processor Internal Architecture
  • Overview of the System Architecture
  • Front Side Bus (FSB)
    • Toggle Mode Transfer Order
    • FSB Electrical Characteristics
    • Intro to the FSB
    • CPU Arbitration
    • Priority Agent Arbitration
    • Request Phase
    • Snoop Phase
    • Response and Data Phases
    • Deferred Transactions
  • Interrupt Delivery
  • Introduction to Some Core Concepts
  • The P6 Core Overview
  • Core 2 Duo
  • Processor PowerOn Configuration
  • Processor Startup
  • The Memory Types
  • Overview of the L1 and L2 Caches
  • Overview of SMM
  • Intel 64 and IA32 Register Set
  • Segmentation in Real Mode
  • Segmentation in Protected Mode
  • Flat Model
  • Paging
  • Task Switching
  • VM86 Mode
  • Virtualization Overview
  • Debug Registers
  • Exceptions
  • Machine Check Architecture
  • Instruction Set Evolution
  • MMX, SSE, SSE2, SSE3 Instruction Set Overview

Recommended Prerequisites: None

Supplied Materials:

MindShare’s x86 Instruction Set Architecture Book or eBook.
Author: Tom Shanley
Publisher: MindShare Press
Available through the MindShare Store and major bookstore outlets.

Students will be provided with an electronic version of the slides used in class.




• Folsom, CA: 5/28/2013

x86 Instruction Set Architecture