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AMD Opteron Processor (Bulldozer)
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Let MindShare Bring AMD OpteronTM Processors to Life for You

The AMD Opteron Processor was the first 64-bit x86-based processor available, implementing the AMD64 instruction set (also known as x86-64). The latest processor family from AMD targeted at the server space is codenamed Bulldozer. These processors are built with multiple Bulldozer "modules," integrated memory controllers, multiple HyperTransport links (Gen3), shared L3 caches, multiple power-planes, etc.

MindShare Courses On AMD Opteron (Bulldozer):

Course Name
Classroom

Virtual Classroom

eLearning
Comprehensive AMD Opteron Processor (Bulldozer)
4 days

5 days
 
Comprehensive x86 APIC Architecture Course
1 day

1 day
Notify Me When Available
Comprehensive AMD 32/64-bit x86 Architecture
3 days

4 days
Notify Me When Available
Intro to 32/64-bit x86 Architecture    
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All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.


Comprehensive AMD Opteron Processor Course Info

You Will Learn:

  • The Bulldozer (Family 15h) microarchitecture
  • Basic behaviors of AMD64
  • How to optimize code for an Opteron processor
  • Basic behavior of the BIOS in discovering and initializing multi-socket systems
  • Performance implications of AMD's multi-core, multi-socket systems
  • Characteristics of the integrated memory controller and effects of a NUMA architecture
  • The protocol and features of HyperTransport (Gen1 and Gen3)

Course Length: 4 Days

Course Outline:

  • Software Architecture
    • Operating Modes
    • Register Set
    • Segmentation
    • Task Management
    • Interrupts and Exceptions
    • AMD64 Paging Mechanisms
    • Instruction Set Extensions (SSE, SSE2, SSE3, SSE4, SSE4a, SSE5, AVX)
    • Virtualization
  • Processor Core Microarchitecture
    • Processor Core Introduction and Terminology
      • Instructions vs Macro-Ops vs Micro-Ops
      • Bulldozer Modules (compute units)
    • The Integer Pipeline
      • Fetch Engine
      • Branch Prediction
      • Scan/Align Logic
      • Instruction Decode
      • Instruction Control Unit
      • Register Renaming
      • Schedulers
      • Execution Units
      • Retirement
    • FPU
      • Register Renaming
      • Scheduling
      • Execution Units
      • Retirement
    • Load/Store Unit
    • The Caches
      • L1 Instruction Cache
      • L1 Data Cache
      • L2 Unified Cache
      • L3 Shared Cache
      • L1 and L2 TLBs
      • MOESI Cache Coherency Protocol
      • Cache probing example
  • System Architecture
    • Example System Topologies
    • System Components on the Chip
    • HyperTransport Overview
      • HyperTransport 1.0
      • HyperTransport 3.0
    • Configuration Space Overview
    • DRAM Technology Overview
      • DDR
      • DDR2
      • DDR3
      • G3MX and FB-DIMM overviews
    • System Power-Up Process
      • BSP Identification and Responsibilities
      • Routing Tables
      • Enumeration I/O Devices
      • HyperTransport Tuning
      • DRAM Address Map
        • NUMA
      • I/O Address Map
      • MMIO Address Map
    • APIC
    • Performance Monitoring Registers
    • Instruction Based Sampling (IBS)
    • Processor Power Management

Recommended Prerequisites: None.

Supplied Materials:

MindShare’s x86 Instruction Set Architecture Book or eBook.
Author: Tom Shanley
Publisher: MindShare Press
Available through the MindShare Store and major bookstore outlets.

Students will be provided with an electronic version of the slides used in class.




x86 Instruction Set Architecture