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ISA System Architecture (3rd Edition)
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Technical Titles
FireWire System Architecture (2nd Edition)
HyperTransport 3.1 Interconnect Technology
HyperTransport System Architecture
InfiniBand Network Architecture
ISA System Architecture (3rd Edition)
PCI Express System Architecture
PCI Express Technology 3.0
PCI System Architecture (4th Edition)
PCI-X System Architecture
SAS Storage Architecture
SATA Storage Technology
The Unabridged Pentium 4
Universal Serial Bus System Architecture
USB 3.0 Technology
x86 Instruction Set Architecture

Historical Titles
Heaven's Favorite - Book One Ascent: The Rise of Chinggis Khan
Heaven's Favorite - Book Two Dominion: Dawn of the Mongol Empire




ISA System Architecture (3rd Edition)

Author(s): Tom Shanley, Don Anderson
Publisher: Addison Wesley
Retail Price: $49.99

eBook Price
$15.00


"A must-have PC architecture reference set."
     - PC Magazine's 'Read Only' Column

ISA System Architecture describes the hardware architecture of ISA (Industry Standard Architecture), providing a clear, concise explanation of an ISA system in detail. This book is divided into three parts:

Part 1: The System Kernel
This section provides a detailed tutorial on how Intel X86 microprocessors communicate with memory and I/O devices. Included is the support logic which allows the microprocessor to communicate with 8- and 16-bit devices and detailed descriptions of the signals and timing involved in all Bus Cycle types.

Part 2: Memory Subsystems
The memory section provides a detailed theory of operation of RAM and ROM devices, along with implementations commonly used in ISA systems. The section also covers the concepts and terminology related to cache memory designs.

Part 3: The Industry Standard Architecture
This section provides a detailed discussion of the ISA Bus Architecture including ISA bus cycles and timing, along with ISA implementations of Interrupts, DMA, Real-Time Clock and Configuration RAM, Numeric Coprocessors, Keyboard/Mouse Interface, and Timers.

Key Topics:

  • Bus cycles
  • Addressing
  • I/O
  • RAM, ROM, and cache memory
  • Cache architectures
  • Decode and reset logic
  • Interrupts
  • System kernel
  • Bus mastering
  • DMA
  • RTC and configuration RAM
  • About the Authors

    Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.

    Don Anderson has over 30 years of experience in the technical electronics and computer industry. He has authored 14 books covering various aspects of computer hardware and system design. Topics include system architectures, parallel bus technologies, serial bus technologies, and processor architectures. Don has trained thousands of engineers in the US and around the world. Before joining MindShare, Don worked for Compaq, Schlumberger, Geosource and Hewlett Packard.