Comprehensive Modern DRAM (DDR2/DDR3) Architecture eLearning Course

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Comprehensive Modern DRAM (DDR2/DDR3) Architecture eLearning Course

Instructor(s): John Swindle
Number of Modules: 20
Subscription Length: 90 days

Course Price

Comprehensive Modern DRAM (DDR2/DDR3) Architecture

What's Included?

DRAM eLearning modules
(unlimited access for 90 days)
PDF of Course Slides
(yours to keep, does not expire)

Benefits of eLearning:

  • Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
  • Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
  • Available 24/7 - MindShare eLearning courses are available when and where you need them
  • Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready

You Will Learn:

  • How a DRAM cell is organized
  • Organization of a variety of memory modules
  • How to read DRAM transaction waveforms so that you can debug a memory channel
  • Electrical characteristics of DDR2/DDR3 signals
  • Elements of DRAM controller design
  • Differences between DDR1, DDR2 and DDR3

Who Should View?

This course is hardware centric but does describe DRAM memory and DRAM controller initialization. It is targeted for hardware engineers, but would also benefit software/firmware engineers. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers.

Course Outline:

  • Introduction and Table of Contents
    - Covers the outline and objectives of the course
  • Chapter 1: System Architecture
    - Discusses where DRAM fits into various x86-based systems
  • Chapter 2: DRAM Feature Summary
    - Provides a history of DRAM and introduces common features of modern DRAM chips
  • Chapter 3: Intro to DRAM
    - Briefly touches on where DRAM came from and provides basic definitions
  • Chapter 4: DRAM Cell Architecture
    - Describes the architecture of an individual cell within a DRAM chip as well as the open cell array architecture, folded cell array architecture and sense amplifiers
  • Chapter 5: DRAM Chip Architecture
    - Describes the internal structure of a DRAM chip including: banks, toggle mode addressing, SDRAM architecture, DDR1, DDR2 and DDR3 architectures, clock speeds and packaging
  • Chapter 6 Part 1: DRAM Modules
    - Covers unbuffered modules, registered modules, ranks, DIMM configurations and module types (UDIMM, RDIMM, SODIMM, FBDIMM, etc.)
  • Chapter 6 Part 2: DRAM Modules
    - Introduces and defines the purpose of each pin for DDR2 and DDR3 modules
  • Chapter 7 Part 1: DDR DRAM Commands and Waveforms
    - Describes bank states and DDR2 and DDR3 Commands
  • Chapter 7 Part 2: DDR DRAM Commands and Waveforms
    - Provides detailed descriptions and waveform diagrams for initialization commands (e.g. mode register set commands) as well as read commands including a discussion on burst transactions and burst order
  • Chapter 7 Part 3: DDR DRAM Commands and Waveforms
    - Covers write commands, precharge, auto precharge, refresh, self refresh, power down, and 1T and 2T timings
  • Chapter 8 Part 1: DDR Initialization
    - Covers the initialization procedure that the DRAM controller must go through prior to using DRAM for normal operation
  • Chapter 8 Part 2: DDR Initialization
    - Covers the role SMBus plays in DRAM and basic operation of SMBus
  • Chapter 9: Electrical Specifications
    - Provides an overview of some of the electrical requirements for DRAM devices
  • Chapter 10: DDR1 and DDR2 Routing
    - Discusses the requirements for routing signals between the DRAM controller and the DDR1 and DDR2 devices (DDR3 routing is covered in Chapter 13)
  • Chapter 11: On-Die Termination
    - Covers on-die termination, off-chip driver calibration and ZQ calibration for DDR2 and DDR3 devices
  • Chapter 12: Errors
    - Describes the sources of errors in DRAM chips and techniques to correct or recover from those errors (ECC, scrubbing, parity, etc.)
  • Chapter 13: Additional DDR3 Topics
    - Covers fly by routing, read calibration, write leveling, the asynchronous reset pin, and On-DIMM mirroring
  • Chapter 14: DRAM Controller Basics
    - Discusses some of the requirements of a DRAM Controller and also discusses how addresses are modified by the DRAM controller
  • Chapter 15: Alternative DRAM Solutions
    - Provides an introduction to other types of DRAM such as Fully-Buffered DIMM (FBDIMM), GDDR, RL DRAM, XDR and LPDDR2

Resources: MindShare DRAM Quick Reference Guide (v5a)


Course Modules
Introduction and Table of Contents22 minutes
Chapter 1: System Architecture20 minutes
Chapter 2: DRAM Feature Summary42 minutes
Chapter 3: Intro to DRAM12 minutes
Chapter 4: DRAM Cell Architecture16 minutes
Chapter 5: DRAM Chip Architecture48 minutes
Chapter 6 Part 1: DRAM Modules40 minutes
Chapter 6 Part 2: DRAM Modules37 minutes
Chapter 7 Part 1: DDR DRAM Commands and Waveforms42 minutes
Chapter 7 Part 2: DDR DRAM Commands and Waveforms42 minutes
Chapter 7 Part 3: DDR DRAM Commands and Waveforms41 minutes
Chapter 8 Part 1: DDR Initialization46 minutes
Chapter 8 Part 2: DDR Initialization11 minutes
Chapter 9: Electrical Specifications10 minutes
Chapter 10: DDR1 and DDR2 Routing18 minutes
Chapter 11: On-Die Termination29 minutes
Chapter 12: Errors24 minutes
Chapter 13: Additional DDR3 Topics44 minutes
Chapter 14: DRAM Controller Basics29 minutes
Chapter 15: Alternative DRAM Solutions11 minutes