[{"data":1,"prerenderedAt":290},["ShallowReactive",2],{"GET-ebooks/slug/sas-storage-architecture-{}-{}":3,"GET-ebooks/asideAll-{}-{}":41},{"id":4,"name":5,"slug":6,"category_id":7,"author":8,"revision":9,"errata_text":10,"errata_link":11,"price":8,"file_path":12,"file_name":13,"cover_url":14,"peek_inside_file":8,"peek_inside_url":8,"overview":15,"has_book":16,"book_out_of_stock":16,"key_topics":17,"about_the_authors":18,"info":19,"authors":20,"publisher":21,"pages":22,"retail_price":23,"ebook_price":24,"book_price":25,"combined_price":25,"tags":26,"price_type":30,"related_items":31,"shipping_details":32,"is_active":35,"meta_title":8,"meta_description":36,"meta_keywords":37,"user_ebook":38},374,"SAS Storage Architecture","sas-storage-architecture",1,null,"1.1","Errata for 1st Edition","https://www.mindshare.com/images/MindShare_SAS_book_errata_2007-7-3.pdf","storage/app/ebooks/legacy/protected/","MindShare_SAS_eBook_v1.1.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/SAS_Storage_Architecture_cover-2025-06-30_15%3A16%3A50.jpg","\u003Cp>MindShare's SAS Storage Architecture book provides an in-depth and comprehensive introduction to the SAS standard. The book contains help for design, verification, and test projects. In addition, it offers valuable insight into the technology's development and features.\u003C/p>\r\n\u003Cp>Following an overview of the SAS architecture, the book moves on to cover transaction protocols, the physical/electrical layers and more. Thoughtfully organized and comprehensive in scope, featuring nearly 300 illustrations, the SAS Storage Architecture book is an essential resource for anyone working with this important technology.\u003C/p>",false,"\u003Cul>\r\n\u003Cli>Background\r\n\u003Cul>\r\n\u003Cli>SCSI, ATA, Fibre Channel\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>SAS Architectural Overview\r\n\u003Cul>\r\n\u003Cli>Serial Operation\u003C/li>\r\n\u003Cli>Definitions\u003C/li>\r\n\u003Cli>Expander Devices\u003C/li>\r\n\u003Cli>Overview of layers\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Upper Layers\r\n\u003Cul>\r\n\u003Cli>Application and Transport Layers\u003C/li>\r\n\u003Cli>SSP, STP, SMP\u003C/li>\r\n\u003Cli>Port Layer\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Link Layer\r\n\u003Cul>\r\n\u003Cli>Primitives\u003C/li>\r\n\u003Cli>Serial Support\u003C/li>\r\n\u003Cli>Frames, Connections, Arbitration\u003C/li>\r\n\u003Cli>SSP, STP and SMP Protocols\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Physical Layers\r\n\u003Cul>\r\n\u003Cli>PHY layer - Encoding, Initialization, OOB\u003C/li>\r\n\u003Cli>Resets\u003C/li>\r\n\u003Cli>Physical layer\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Appendices\r\n\u003Cul>\r\n\u003Cli>SCSI background\u003C/li>\r\n\u003Cli>Fibre Channel background\u003C/li>\r\n\u003Cli>Sharing the server market: SAS, SATA, and Fibre Channel\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","\u003Cp>Mike Jackson is a senior staff engineer and instructor with MindShare, Inc., where he has trained thousands of engineers. He is an industry expert on such topics as Intel Processor and PC architecture, as well as such bus architectures as SAS, PCI, PCI-X, and PCI Express. Before joining MindShare, Mr. Jackson worked as a high-speed digital designer for AMD and as an ASIC developer for several years with Compaq Computer Corp.\u003C/p>","\u003Cp>\"STA is delighted to have had the opportunity to contribute to MindShare's SAS Storage Architecture book. SAS technology is a significant inflection point in the evolution of data storage and MindShare has done an admirable job in explaining the technology. The content of the MindShare book will be very beneficial to SAS system designers and integrators and also provide a valuable resource for engineering students.\"\u003Cbr>     - Harry Mason, President of the SCSI Trade Association\u003C/p>","Mike Jackson","MindShare Press",630,"69.99","30","0",[27],{"id":28,"name":29,"tag_type":7},6,"Storage","ebook_price",[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":34},0.01,0.003,true,"MindShare SAS book","sas, serial attached scsi, mindshare, book",{"id":39,"presentation_id":8,"downloaded":16,"signed_file_name":8,"watermark_status":40,"is_new":16,"revision":8},63755,"WATERMARK_NOT_CREATED",{"data":42},[43,68,114,136,156,177,183,201,221,238,253,273],{"id":44,"name":45,"slug":46,"category_id":7,"author":8,"revision":47,"errata_text":48,"errata_link":49,"price":8,"file_path":12,"file_name":50,"cover_url":51,"peek_inside_file":8,"peek_inside_url":8,"overview":52,"has_book":16,"book_out_of_stock":16,"key_topics":53,"about_the_authors":54,"info":55,"authors":56,"publisher":21,"pages":57,"retail_price":58,"ebook_price":59,"book_price":25,"combined_price":25,"tags":60,"price_type":30,"related_items":61,"shipping_details":62,"is_active":35,"meta_title":64,"meta_description":64,"meta_keywords":65,"user_ebook":66},381,"PCI Express Technology 3.0","pci-express-technology-30","1.03","Errata as of November 12, 2017 (First Printing and eBook up to v1.02)","https://www.mindshare.com/images/PCIe_3.0_Errata_November_12_2017.pdf","MindShare_PCIe30_eBook_v1.03.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/PCI_Express_Technology_3.0_cover-2025-06-30_15%3A23%3A39.jpg","\u003Cp>PCI Express 3.0 is the latest generation of the popular peripheral interface found in virtually every PC, server, and industrial computer. Its high bandwidth, low latency, and cost-to-performance ratio make it a natural choice for many peripheral devices today. Each new generation of PCI Express adds more features, capabilities and bandwidth, which maintains its popularity as a device interconnect.\u003Cbr>\u003Cbr>MindShare's books take the hard work out of deciphering the specs, and this one follows that tradition. MindShare's \u003Cem>PCI Express Technology\u003C/em> book provides a thorough description of the interface with numerous practical examples that illustrate the concepts. Written in a tutorial style, this book is ideal for anyone new to PCI Express. At the same time, its thorough coverage of the details makes it an essential resource for seasoned veterans.\u003C/p>","\u003Cul>\r\n\u003Cli>PCI Express Origins\u003C/li>\r\n\u003Cli>Configuration Space and Access Methods\u003C/li>\r\n\u003Cli>Enumeration Process\u003C/li>\r\n\u003Cli>Packet Types and Fields\u003C/li>\r\n\u003Cli>Transaction Ordering\u003C/li>\r\n\u003Cli>Traffic Classes, Virtual Channels and Arbitration (QoS)\u003C/li>\r\n\u003Cli>Flow Control\u003C/li>\r\n\u003Cli>ACK/NAK Protocol\u003C/li>\r\n\u003Cli>Logical PHY (8b/10b, 128b/130b, Scrambling)\u003C/li>\r\n\u003Cli>Electrical PHY\u003C/li>\r\n\u003Cli>Link Training and Initialization\u003C/li>\r\n\u003Cli>Interrupt Delivery (Legacy, MSI, MSI-X)\u003C/li>\r\n\u003Cli>Error Detection and Reporting\u003C/li>\r\n\u003Cli>Power Management (for both software and hardware)\u003C/li>\r\n\u003Cli>2.0 and 2.1 Features (such as 5.0GT/s, TLP Hints, and Multi-Casting)\u003C/li>\r\n\u003Cli>3.0 Features (such as 8.0GT/s, and a new encoding scheme)\u003C/li>\r\n\u003Cli>Considerations for High Speed Signaling (such as Equalization)\u003C/li>\r\n\u003C/ul>","\u003Cp class=\"body\">\u003Cstrong>Mike Jackson\u003C/strong>, is a senior staff engineer and instructor with MindShare, Inc., where he has trained thousands of engineers. He is an industry expert on such topics as Intel Processor and PC architecture, as well as such bus architectures as SAS, PCI, PCI-X, and PCI Express. Before joining MindShare, Mr. Jackson worked as a high-speed digital designer for AMD and as an ASIC developer for several years with Compaq Computer Corp.\u003C/p>\r\n\u003Cp class=\"body\">\u003Cstrong>Ravi Budruk\u003C/strong> is a partial owner and instructor with MindShare, Inc., where he has trained hundreds of engineers. He is an industry expert on such topics as Intel processors and PC architecture, as well as such bus architectures as PCI Express, PCI, PCI-X, HyperTransport, IEEE 1394, and ISA. Before working at MindShare, Mr. Budruk was a PC chipset architect and designer at VLSI Technology, Inc.\u003C/p>","\u003Cp>“MindShare books are critical in the understanding of complex technical topics, such as PCI Express 3.0 architecture. Many of our customers and industry partners depend on these books for the success of their projects.”\u003Cbr>\u003Cbr>— Joe Mendolia - Vice President, LeCroy\u003C/p>","Mike Jackson, Ravi Budruk",1056,"94.99","40",[],[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":63},0.006,"MindShare PCI Express 3.0 book","pcie, pci express, 3.0, book",{"id":67,"presentation_id":8,"downloaded":16,"signed_file_name":8,"watermark_status":40,"is_new":16,"revision":8},34240,{"id":69,"name":70,"slug":71,"category_id":7,"author":8,"revision":72,"errata_text":73,"errata_link":74,"price":8,"file_path":75,"file_name":76,"cover_url":77,"peek_inside_file":8,"peek_inside_url":8,"overview":78,"has_book":16,"book_out_of_stock":16,"key_topics":79,"about_the_authors":80,"info":81,"authors":82,"publisher":21,"pages":83,"retail_price":84,"ebook_price":24,"book_price":25,"combined_price":25,"tags":85,"price_type":30,"related_items":89,"shipping_details":8,"is_active":35,"meta_title":8,"meta_description":110,"meta_keywords":111,"user_ebook":112},382,"USB 3.0 Technology","usb-30-technology","1.02","Errata as of February 21, 2014","https://www.mindshare.com/images/MindShare_USB3.0_Errata_2-21-2014.pdf","storage/app/ebooks/","MindShare_USB3.0_eBook_v1.02.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/USB_3.0_Technology_cover-2025-06-30_15%3A24%3A41.jpg","\u003Cp>The third generation of USB increases transfer rates to 5.0 Gbits/s (SuperSpeed) and includes backward compatibility with all earlier USB specifications (1.1/2.0) and speeds (Low Speed, Full Speed, and High Speed) USB 3.0 SuperSpeed protocol also brings significant enhancements in the areas of device and system power conservation, error handling, and data flow control.\u003Cbr>\u003Cbr>SuperSpeed bus instances replace the USB broadcast bus model with directed (unicast) packets. Dual-simplex signaling enables asynchronous device notifications and simplifies link partner communication used in link flow control, packet acknowledgement and retry, and power management transitions.\u003Cbr>\u003Cbr>MindShare's books take the hard work out of deciphering the specs, and this one follows that tradition. MindShare's USB 3.0 Technology book provides a thorough description of the interface with numerous practical examples that illustrate the concepts. Written in a tutorial style, this book is ideal for anyone working with USB technologies.\u003C/p>","\u003Cul>\r\n\u003Cli>Motivations for USB 3.0\u003C/li>\r\n\u003Cli>End-to-End Protocols\u003C/li>\r\n\u003Cli>Protocol Packet Types and Fields\u003C/li>\r\n\u003Cli>Transfer Types\u003C/li>\r\n\u003Cli>Bulk Streaming\u003C/li>\r\n\u003Cli>Port-to-Port Protocols\u003C/li>\r\n\u003Cli>Link Packet Types and Fields\u003C/li>\r\n\u003Cli>Link and Physical Layer Hardware\u003C/li>\r\n\u003Cli>Link Flow Control\u003C/li>\r\n\u003Cli>Link Error Detection and Handling\u003C/li>\r\n\u003Cli>8b/10b Encoding/Decoding\u003C/li>\r\n\u003Cli>Ordered Sets\u003C/li>\r\n\u003Cli>Link Power Management\u003C/li>\r\n\u003Cli>SuperSpeed Reset\u003C/li>\r\n\u003Cli>Link Initialization\u003C/li>\r\n\u003Cli>USB Configuration\u003C/li>\r\n\u003Cli>USB 3.0 Hubs\u003C/li>\r\n\u003Cli>Physical Layer Electrical\u003C/li>\r\n\u003Cli>Compliance Testing\u003C/li>\r\n\u003C/ul>","\u003Cp class=\"body\">\u003Cstrong>Donovan (Don) Anderson\u003C/strong>, has worked with MindShare for over 21 years and has conducted courses on a wide range of topics including USB and has authored/co-authored 14 MindShare books including USB 2.0 System Architecture and PCI Express.\u003C/p>\r\n\u003Cp class=\"body\">\u003Cstrong>Jay Trodden\u003C/strong> has been a computer hardware designer for many years and a MindShare instructor for nearly 14 years. His design and teaching experience includes work with many processors and a number of bus architectures, including PCI, PCI-X, PCI Express, HyperTransport, and USB. Jay co-authored MindShare's HyperTransport System Architecture book.\u003C/p>","\u003Cp>\"A critical success factor in developing high-speed serial data protocols is ramping up on these technologies quickly. We have found that MindShare books, like USB 3.0 Technology, allow engineers to learn new protocols more quickly and efficiently compared to reading the specifications.\"\u003Cbr>\u003Cbr>- Mike Micheletti - USB Product Manager, Teledyne LeCroy\u003C/p>","Don Anderson, Jay Trodden",650,"74.99",[86],{"id":87,"name":88,"tag_type":7},2,"USB",[90,97,104],{"id":91,"name":92,"slug":93,"price":94,"model":95,"cover_url":96},368,"Universal Serial Bus System Architecture","universal-serial-bus-system-architecture","20","ebooks","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/Universal_Serial_Bus_System_Architecture_cover-2025-06-30_15%3A08%3A51.jpg",{"id":98,"name":99,"slug":100,"price":101,"model":102,"cover_url":103},1719,"xHCI eLearning Course","xhci-elearning-course","395","elearning_courses","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/xHCI_eLearning_Course_thumbnail.png",{"id":105,"name":106,"slug":107,"price":108,"model":102,"cover_url":109},1730,"USB Type-C and Power Delivery eLearning Course","usb-type-c-and-power-delivery-elearning-course","295","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/USB_Type-C_and_Power_Delivery_eLearning_Course_thumbnail.png","usb 3.0 book","usb 3.0, superspeed usb, mindshare, book, ebook",{"id":113,"presentation_id":8,"downloaded":16,"signed_file_name":8,"watermark_status":40,"is_new":16,"revision":8},34226,{"id":115,"name":116,"slug":117,"category_id":7,"author":8,"revision":118,"errata_text":8,"errata_link":8,"price":8,"file_path":12,"file_name":119,"cover_url":120,"peek_inside_file":8,"peek_inside_url":8,"overview":121,"has_book":16,"book_out_of_stock":16,"key_topics":122,"about_the_authors":123,"info":124,"authors":125,"publisher":21,"pages":126,"retail_price":127,"ebook_price":59,"book_price":25,"combined_price":25,"tags":128,"price_type":30,"related_items":129,"shipping_details":130,"is_active":35,"meta_title":8,"meta_description":132,"meta_keywords":133,"user_ebook":134},380,"x86 Instruction Set Architecture","x86-instruction-set-architecture","1.0","MindShare_x86_ISA_eBook_v1.0.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/x86_Instruction_Set_Architecture_cover-2025-06-30_15%3A22%3A18.png","\u003Cp>Wikipedia Definition: The Instruction Set Architecture, or ISA, is defined as that part of the processor architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external IO.\u003Cbr>\u003Cbr>Except for some small deviations and differences in terminology, all Intel and AMD x86 processors share a common ISA. This book focuses on those shared attributes (it does not cover those areas where the two companies have chosen widely divergent solutions, which, by definition, fall outside of the ISA specification).\u003Cbr>\u003Cbr>If you’re looking for a comprehensive book designed to bootstrap you up quickly on virtually all aspects of the x86 32/64-bit Instruction Set Architecture (ISA), we respectfully ask you to consider this book. Tom Shanley, President of MindShare, Inc., applied his 40 years of hardware and software experience with Intel processors (from the 4004 and 8008 through the Nehalem-based processors of today) to this ambitious undertaking. The material organization is derived from those used to train thousands of software and hardware designers at virtually all of the world’s leading high-tech companies.\u003C/p>","\u003Cul>\r\n\u003Cli>Basic Terms and Concepts\u003C/li>\r\n\u003Cli>Mode/SubMode Introduction\u003C/li>\r\n\u003Cli>A (very) Brief History\u003C/li>\r\n\u003Cli>State After Reset\u003C/li>\r\n\u003Cli>Intro to the IA-32 Ecosystem\u003C/li>\r\n\u003Cli>Instruction Set Expansion\u003C/li>\r\n\u003Cli>32-bit Machine Language Instruction Format\u003C/li>\r\n\u003Cli>Real Mode (8086 Emulation)\u003C/li>\r\n\u003Cli>Legacy x87 FP Support\u003C/li>\r\n\u003Cli>Introduction to Multitasking\u003C/li>\r\n\u003Cli>Multitasking-Related Issues\u003C/li>\r\n\u003Cli>Summary of the Protection Mechanisms\u003C/li>\r\n\u003Cli>Protected Mode Memory Addressing\u003C/li>\r\n\u003Cli>Code, Calls and Privilege Checks\u003C/li>\r\n\u003Cli>Data and Stack Segments\u003C/li>\r\n\u003Cli>IA-32 Address Translation Mechanisms\u003C/li>\r\n\u003Cli>Memory Type Configuration\u003C/li>\r\n\u003Cli>Task Switching\u003C/li>\r\n\u003Cli>Protected Mode Interrupts and Exceptions\u003C/li>\r\n\u003Cli>Virtual 8086 Mode\u003C/li>\r\n\u003Cli>The MMX Facilities\u003C/li>\r\n\u003Cli>The SSE Facilities\u003C/li>\r\n\u003Cli>IA-32e OS Environment\u003C/li>\r\n\u003Cli>IA-32e Address Translation\u003C/li>\r\n\u003Cli>Compatibility Mode\u003C/li>\r\n\u003Cli>64-bit Register Overview\u003C/li>\r\n\u003Cli>64-bit Operands and Addressing\u003C/li>\r\n\u003Cli>64-bit Machine Language Instruction Format\u003C/li>\r\n\u003Cli>64-bit Odds and Ends\u003C/li>\r\n\u003Cli>Transitioning to Protected Mode\u003C/li>\r\n\u003Cli>Transitioning to IA-32e Mode\u003C/li>\r\n\u003Cli>Introduction to Virtualization Technology\u003C/li>\r\n\u003Cli>System Management Mode (SMM)\u003C/li>\r\n\u003Cli>Machine Check Architecture (MCA)\u003C/li>\r\n\u003Cli>The Local and IO APICs\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cstrong>Tom Shanley\u003C/strong>, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.\u003C/p>","\u003Cp>Processor design-specific subjects such as Power Management and design-specific MSRs are not covered in this book. Rather, they are covered in MindShare's Processor family-specific microarchitecture classes.\u003C/p>\r\n\u003Cp>MindShare's System Architecture Series is a crisply written and comprehensive set of guides to the most important computer hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.\u003C/p>","Tom Shanley",1567,"99.99",[],[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":131},0.008,"MindShare x86 Instruction Set Architecture","x86, intel architecture, amd64, ia-32, intel 64, book, ebook, e-book",{"id":135,"presentation_id":8,"downloaded":16,"signed_file_name":8,"watermark_status":40,"is_new":16,"revision":8},93253,{"id":137,"name":138,"slug":139,"category_id":7,"author":8,"revision":118,"errata_text":8,"errata_link":8,"price":8,"file_path":12,"file_name":140,"cover_url":141,"peek_inside_file":8,"peek_inside_url":8,"overview":142,"has_book":16,"book_out_of_stock":16,"key_topics":143,"about_the_authors":144,"info":145,"authors":146,"publisher":21,"pages":147,"retail_price":148,"ebook_price":24,"book_price":25,"combined_price":25,"tags":149,"price_type":30,"related_items":150,"shipping_details":151,"is_active":35,"meta_title":8,"meta_description":153,"meta_keywords":154,"user_ebook":155},378,"HyperTransport 3.1 Interconnect Technology","hypertransport-31-interconnect-technology","MindShare_HyperTransport_3.1_eBook_v1.0.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/HyperTransport_3.1_Interconnect_Technology_cover-2025-06-30_15%3A18%3A50.jpg","\u003Cp>HyperTransport System Architecture provides a comprehensive technical guide to the HyperTransport Technology. It opens with an overview of HT, highlighting features of the technology’s fundamental architecture, including its many advantages over other bus architectures. The book then goes on to detail all facets of the HyperTransport Technology including protocol, I/O routing, configuration and more. In particular, it features important performance related considerations and addresses critical compatibility issues. An entire section provides numerous transaction examples to illustrate the practical application of the HyperTransport Technology. HyperTransport System Architecture provides the authoritative, detailed information required by hardware and software developers, networking professionals and anyone interested in implementing and deploying HyperTransport.\u003C/p>","\u003Cul>\r\n\u003Cli>Packet protocol, including control and data packets\u003C/li>\r\n\u003Cli>HT flow control and how it differs from PCI flow control\u003C/li>\r\n\u003Cli>I/O ordering rules: Upstream, Downstream, and Host\u003C/li>\r\n\u003Cli>Interrupts, Error detection and handling\u003C/li>\r\n\u003Cli>HT System Management\u003C/li>\r\n\u003Cli>Routing packets, including the fairness algorithm\u003C/li>\r\n\u003Cli>Configuration and PCI, PCI-X, AGP and X86 compatibility issues\u003C/li>\r\n\u003Cli>The Electrical Environment\u003C/li>\r\n\u003Cli>Network Extensions\u003C/li>\r\n\u003Cli>HyperTransport bridges\u003C/li>\r\n\u003Cli>Double-hosted chains\u003C/li>\r\n\u003C/ul>","\u003Cp>Jay Trodden is an electrical engineer with over 15 years experience in electronics hardware design. For the past 10 years he has been teaching and developing courses on processors and IO bus architectures for MindShare.\u003C/p>\r\n\u003Cp class=\"body\">\u003Cstrong>Don Anderson\u003C/strong> has 29 year's combined development experience in analog and digital electronics and the computer industry, working for companies such as Hewlett Packard, Schlumberger, and Compaq. Since joining MindShare in 1991, he has authored and co-authored 12 books on PC Architecture and has taught over 500 courses.\u003C/p>","\u003Cp>\"A must-have PC architecture reference set.\"\u003Cbr>     - PC Magazine's 'Read Only' Column\u003C/p>","Brian Holden, Jay Trodden, Don Anderson",692,"79.99",[],[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":152},0.005,"MindShare HyperTransport 3.1 book","hypertransport, HT, 3.0, 3.1 book, ebook, mindshare",[],{"id":157,"name":158,"slug":159,"category_id":7,"author":8,"revision":9,"errata_text":160,"errata_link":8,"price":8,"file_path":12,"file_name":161,"cover_url":162,"peek_inside_file":8,"peek_inside_url":8,"overview":163,"has_book":16,"book_out_of_stock":16,"key_topics":164,"about_the_authors":165,"info":166,"authors":167,"publisher":21,"pages":168,"retail_price":169,"ebook_price":24,"book_price":25,"combined_price":25,"tags":170,"price_type":30,"related_items":171,"shipping_details":172,"is_active":35,"meta_title":8,"meta_description":173,"meta_keywords":174,"user_ebook":175},376,"SATA Storage Technology","sata-storage-technology","Errata as of May, 8, 2017","MindShare_SATA_eBook_v1.1.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/SATA_Storage_Technology_cover-2025-06-30_15%3A19%3A29.jpg","\u003Ci>SATA Storage Technology\u003C/i> provides ATA background information necessary to understand the Serial ATA implementation. This book provides detailed information regarding the serial protocol, commands, and electrical interface.","\u003Cp>The SATA (Serial ATA) interface is intended to expand and eventually replace the parallel ATA interface that has been the standard connection for hard drives and CD-ROM/DVD drives in Personal Computers for nearly twenty years. SATA, a high-speed serial version of ATA, is designed to maintain compatibility with software written for the standard ATA implementation, thus easing the transition to SATA. New advances in SATA provide new capabilities such as Native Command Queuing that improve overall drive performance and greater reliability. In addition, the latest version of SATA (called SATA II) adds new features such as higher transfer rates, Port Selectors, Port Multipliers, and enclosure services, making it easier to implement low cost, high capacity, storage subsystems for server implementations. This book provides essential information for Systems Engineers, System Validation Engineers, Hardware Designers, and Software Developers.\u003Cbr>\u003Cspan style=\"font-style: italic;\">SATA Storage Technology\u003C/span> provides ATA background information necessary to understand the Serial ATA implementation. This book provides detailed information regarding the serial protocol, commands, and electrical interface. A tutorial approach is taken to facilitate thorough understanding, using numerous illustrations, tables and examples. The text is also designed to provide easy to access valuable reference information.\u003Cbr>\u003Cbr>Book Chapters\u003C/p>\r\n\u003Cul>\r\n\u003Cli>The Evolution of Parallel ATA\u003C/li>\r\n\u003Cli>The Motivation for SATA\u003C/li>\r\n\u003Cli>SATA Overview\u003C/li>\r\n\u003Cli>Introduction to FIS Transfers\u003C/li>\r\n\u003Cli>FIS Types and Formats\u003C/li>\r\n\u003Cli>Transport and Link Protocols\u003C/li>\r\n\u003Cli>FIS Retry\u003C/li>\r\n\u003Cli>Data Flow Control\u003C/li>\r\n\u003Cli>Physical Layer Functions\u003C/li>\r\n\u003Cli>Error Detection\u003C/li>\r\n\u003Cli>The Command Protocol\u003C/li>\r\n\u003Cli>The Control Protocol\u003C/li>\r\n\u003Cli>Sata II Features\u003C/li>\r\n\u003Cli>Native Command Queuing\u003C/li>\r\n\u003Cli>Port Multipliers\u003C/li>\r\n\u003Cli>Port Selectors\u003C/li>\r\n\u003Cli>Enclosure Services\u003C/li>\r\n\u003Cli>SATA Initialization\u003C/li>\r\n\u003Cli>Physical Layer\u003C/li>\r\n\u003Cli>Form Factors\u003C/li>\r\n\u003Cli>Hot Plug\u003C/li>\r\n\u003Cli>Link Power Management\u003C/li>\r\n\u003Cli>BIST Features\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cspan style=\"font-weight: bold;\">Don Anderson\u003C/span> has over 30 years of experience in the technical electronics and computer industry. He has authored of fourteen books covering various aspects of computer hardware and system design. Topics include system architectures, parallel bus technologies, serial bus technologies, and processor architectures. Don has trained thousands of engineers in the US and around the world. Before joining MindShare, Don worked for Compaq, Schlumberger, Geosource and Hewlett Packard.\u003Cbr>\u003Cbr>\u003Cspan style=\"font-weight: bold;\">MindShare, Inc.\u003C/span> was founded in 1988 to bring computer architecture-related training to the hardware and software design communities. Since then, we have expanded our course offerings to include SAS™, SATA™, iSCSI, Fibre Channel, PCI Express™, PCI-X™, PCI™ and HyperTransport™ System Architectures as well as Pentium 4 and Opteron Processor Architectures. \u003Cbr>\u003Cbr>MindShare instructors travel the world delivering customized training courses to the very companies that lead the high-tech industry. Our instructors have tremendous computer engineering experience. Our consistent research and training efforts ensure that instructors and authors are always up to date on the latest technological trends.\u003C/p>","\u003Cp>\"This SATA Storage Technology book from MindShare is the ultimate tutorial on the SATA specification and its implementation. Any SATA-based product developer will find the clear and concise explanations of the various features found in this protocol to be invaluable. Particular emphasis is placed on the sections of the spec that enable SATA to be such an important interface for enterprise storage systems.\"\u003Cbr>     - Mark Adams, Product Marketing Manager of the LeCroy Corporation\u003C/p>","Don Anderson",496,"59.99",[],[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":34},"MindShare SATA book","sata, serial ata, book, mindshare",{"id":176,"presentation_id":8,"downloaded":16,"signed_file_name":8,"watermark_status":40,"is_new":16,"revision":8},63756,{"id":4,"name":5,"slug":6,"category_id":7,"author":8,"revision":9,"errata_text":10,"errata_link":11,"price":8,"file_path":12,"file_name":13,"cover_url":14,"peek_inside_file":8,"peek_inside_url":8,"overview":15,"has_book":16,"book_out_of_stock":16,"key_topics":17,"about_the_authors":18,"info":19,"authors":20,"publisher":21,"pages":22,"retail_price":23,"ebook_price":24,"book_price":25,"combined_price":25,"tags":178,"price_type":30,"related_items":180,"shipping_details":181,"is_active":35,"meta_title":8,"meta_description":36,"meta_keywords":37,"user_ebook":182},[179],{"id":28,"name":29,"tag_type":7},[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":34},{"id":39,"presentation_id":8,"downloaded":16,"signed_file_name":8,"watermark_status":40,"is_new":16,"revision":8},{"id":91,"name":92,"slug":93,"category_id":7,"author":8,"revision":118,"errata_text":10,"errata_link":184,"price":8,"file_path":12,"file_name":185,"cover_url":96,"peek_inside_file":8,"peek_inside_url":8,"overview":186,"has_book":16,"book_out_of_stock":16,"key_topics":187,"about_the_authors":188,"info":145,"authors":167,"publisher":189,"pages":190,"retail_price":191,"ebook_price":94,"book_price":25,"combined_price":25,"tags":192,"price_type":30,"related_items":194,"shipping_details":8,"is_active":35,"meta_title":8,"meta_description":198,"meta_keywords":199,"user_ebook":200},"https://www.mindshare.com/images/USB%201st%20Edition%20Book%20Errata.pdf","MindShare_USB_eBook_v1.0.pdf","\u003Cp>MindShare's Second Edition of their \u003Cem>\u003Cstrong>USB System Architecture\u003C/strong>\u003C/em> book, based on the 2.0 version of the Universal Serial Bus specification, provides in-depth coverage and a detailed discussion of USB. It focuses on the USB protocol, signaling environment, and electrical specifications, along with the hardware/software interaction required to configure and access USB devices. The USB 2.0 specification defines high-speed transactions operating at 480Mb/s that increase throughput by a factor of 40 over the older USB devices. New high-bandwidth, ping, and split transactions have also been added to further increase efficiency of the high-speed protocol. The USB 2.0 specification makes major improvements to USB, while maintaining backward compatibility with 1.0 and 1.1 USB devices. Universal Serial Bus System Architecture, Second Edition, is an essential, time-saving tool. The accompanying CD-ROM includes an 85-minute USB 2.0 overview video by Don Anderson, featuring an introduction to the basic concepts underlying USB 2.0 bus operation and protocol.\u003Cbr>\u003Cbr>Following an overview of the USB architecture, the book next covers low- and full-speed device operation followed by high-speed device operation and configuration.\u003Cbr>\u003Cbr>Note: This book does not cover SuperSpeed USB. For that topic please check out our book on \u003Ca href=\"https://www.mindshare.com/shop/?c=b&section=132B00B5067E\">USB 3.0 Technology\u003C/a>\u003C/p>","\u003Cul>\r\n\u003Cli>Hot plug support (detection of low-, full-, and high-speed devices) Electrical signaling at the 1.5, 12, and 480Mb/s rates\u003C/li>\r\n\u003Cli>2.0 hub operation (including split transaction support)\u003C/li>\r\n\u003Cli>2.0 high-speed protocol (including high-bandwidth and ping transactions)\u003C/li>\r\n\u003Cli>High-speed transceiver test modes\u003C/li>\r\n\u003Cli>Suspend/resume operations\u003C/li>\r\n\u003Cli>Device descriptors *Device requests (commands)\u003C/li>\r\n\u003Cli>USB transaction protocols (low-, full-, and high-speed)\u003C/li>\r\n\u003Cli>Bus-powered devices\u003C/li>\r\n\u003Cli>Self-powered devices\u003C/li>\r\n\u003Cli>Error detection and handling\u003C/li>\r\n\u003Cli>Device configuration\u003C/li>\r\n\u003Cli>Device classes\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cstrong>Don Anderson\u003C/strong> has 29 year's combined development experience in analog and digital electronics and the computer industry, working for companies such as Hewlett Packard, Schlumberger, and Compaq. Since joining MindShare in 1991, he has authored and co-authored 12 books on PC Architecture and has taught over 500 courses.\u003C/p>","Addison Wesley",505,"64.99",[193],{"id":87,"name":88,"tag_type":7},[195,196,197],{"id":69,"name":70,"slug":71,"price":24,"model":95,"cover_url":77},{"id":98,"name":99,"slug":100,"price":101,"model":102,"cover_url":103},{"id":105,"name":106,"slug":107,"price":108,"model":102,"cover_url":109},"MindShare USB book","usb, book, usb 2.0, mindshare",[],{"id":202,"name":203,"slug":204,"category_id":7,"author":8,"revision":118,"errata_text":10,"errata_link":205,"price":8,"file_path":12,"file_name":206,"cover_url":207,"peek_inside_file":8,"peek_inside_url":8,"overview":208,"has_book":16,"book_out_of_stock":16,"key_topics":209,"about_the_authors":123,"info":210,"authors":125,"publisher":189,"pages":211,"retail_price":148,"ebook_price":24,"book_price":25,"combined_price":25,"tags":212,"price_type":30,"related_items":216,"shipping_details":217,"is_active":35,"meta_title":8,"meta_description":218,"meta_keywords":219,"user_ebook":220},369,"The Unabridged Pentium 4","the-unabridged-pentium-4","https://www.mindshare.com/images/P4Errata-4.pdf","MindShare_Pentium4_eBook_v1.0.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/The_Unabridged_Pentium_4_cover-2025-06-30_15%3A09%3A24.jpg","\u003Cp>The Unabridged Pentium 4: IA32 Processor Genealogy book provides an in-depth description and comprehensive reference to the Intel IA32 processor family. This book takes the evolutionary approach in describing the growth of the IA32 processor hardware and software architecture starting with the 386 processor and covering through the Pentium 4 with the Prescott instruction set extensions, the Pentium M and the Pentium 4 Xeon processors.\u003C/p>","\u003Cul>\r\n\u003Cli>Single Task/Multitasking OS Background\u003C/li>\r\n\u003Cli>32-bit Register Set\u003C/li>\r\n\u003Cli>Real Mode\u003C/li>\r\n\u003Cli>Protected Mode\u003C/li>\r\n\u003Cli>Instruction Set\u003C/li>\r\n\u003Cli>Virtual 8086 Mode\u003C/li>\r\n\u003Cli>Demand Mode Paging\u003C/li>\r\n\u003Cli>Interrupts and Exceptions\u003C/li>\r\n\u003Cli>APIC Subsystem\u003C/li>\r\n\u003Cli>Evolution of the IA32 Processors\u003C/li>\r\n\u003Cli>Overview of the P6 Core\u003C/li>\r\n\u003Cli>The P6 FSB operation\u003C/li>\r\n\u003Cli>Processor Power Management\u003C/li>\r\n\u003Cli>Pentium 4 Road Map\u003C/li>\r\n\u003Cli>Pentium 4 System Overview\u003C/li>\r\n\u003Cli>Pentium 4 Processor Overview\u003C/li>\r\n\u003Cli>Pentium 4 PowerOn Configuration\u003C/li>\r\n\u003Cli>Pentium 4 Processor Startup\u003C/li>\r\n\u003Cli>Pentium 4 Core Description\u003C/li>\r\n\u003Cli>Hyper-Threading\u003C/li>\r\n\u003Cli>The Pentium 4 Caches\u003C/li>\r\n\u003Cli>Pentium 4 Handling of Loads and Stores\u003C/li>\r\n\u003Cli>The Pentium 4 Prescott\u003C/li>\r\n\u003Cli>Pentium 4 FSB Electrical Characteristics\u003C/li>\r\n\u003Cli>Intro to the Pentium 4 FSB\u003C/li>\r\n\u003Cli>Pentium 4 CPU Arbitration\u003C/li>\r\n\u003Cli>Pentium 4 Priority Agent Arbitration\u003C/li>\r\n\u003Cli>Pentium 4 Locked Transaction Series\u003C/li>\r\n\u003Cli>Pentium 4 FSB Blocking\u003C/li>\r\n\u003Cli>Pentium 4 FSB Request Phase\u003C/li>\r\n\u003Cli>Pentium 4 FSB Snoop Phase\u003C/li>\r\n\u003Cli>Pentium 4 FSB Response and Data Phases\u003C/li>\r\n\u003Cli>Pentium 4 FSB Transaction Deferral\u003C/li>\r\n\u003Cli>Pentium 4 FSB IO Transactions\u003C/li>\r\n\u003Cli>Pentium 4 FSB Central Agent Transactions\u003C/li>\r\n\u003Cli>Pentium 4 FSB Miscellaneous Signals\u003C/li>\r\n\u003Cli>Pentium 4 Software Enhancements\u003C/li>\r\n\u003Cli>Pentium 4 Xeon Features\u003C/li>\r\n\u003Cli>System Management Mode (SMM)\u003C/li>\r\n\u003C/ul>","\u003Cp>“In this monumental new book, Tom Shanley pulls together 15 years of history of Intel's mainline microprocessors, the most popular and important computer architecture in history. Shanley has a keen eye for the salient facts, and an outstanding sense for how to organize and display the material for easy accessibility by the reader. If you want to know what does this bit control, what does that feature do, and how did those instructions evolve through several generations of x86, this is the reference book for you. This is the book Intel should have written, but now they don't have to.”\u003Cbr>\u003Cbr>—Bob Colwell, former Chief Architect of Intel's IA32 microprocessors from 1992-2000\u003C/p>",1741,[213],{"id":214,"name":215,"tag_type":7},91,"Hardware",[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":131},"MindShare Intel processor book","pentium 4, ia32, processor, intel, mindshare, book",[],{"id":222,"name":223,"slug":224,"category_id":7,"author":8,"revision":225,"errata_text":8,"errata_link":8,"price":8,"file_path":12,"file_name":226,"cover_url":227,"peek_inside_file":8,"peek_inside_url":8,"overview":228,"has_book":16,"book_out_of_stock":16,"key_topics":229,"about_the_authors":230,"info":145,"authors":231,"publisher":189,"pages":232,"retail_price":191,"ebook_price":94,"book_price":25,"combined_price":25,"tags":233,"price_type":30,"related_items":234,"shipping_details":8,"is_active":35,"meta_title":8,"meta_description":235,"meta_keywords":236,"user_ebook":237},373,"PCI System Architecture (4th Edition)","pci-system-architecture-4th-edition","1.01","MindShare_PCI_4th_eBook_v1.01.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/PCI_System_Architecture_%284th_Edition%29_cover-2025-06-30_15%3A15%3A48.jpg","\u003Cp>MindShare's PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification. Intel’s technology for fast communication between peripheral devices and the computer processor.\u003C/p>\r\n\u003Cp>This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification, revisions to the PCI Bus Power Management Interface Specification, and the new features of the PCI BIOS Specification.\u003C/p>\r\n\u003Cp>This book provides clear and concise explanations of the relationship of PCI to the rest of the system and PCI fundamentals, including commands, read and write transfers, memory and I/O addressing, error handling, interrupts, and configuration transactions and registers.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>Changes from PCI 2.1 to PCI 2.2 and changes from PCI-to-PCI Bridge Specification 1.0 to 1.1 are visibly highlighted throughout the book so that those familiar with the previous versions can quickly get a handle on new features and functions.\u003C/p>\r\n\u003Cp>Anyone who designs or tests hardware or software involving the PCI bus will find PCI System Architecture, Fourth Edition a valuable resource for understanding and working with this important technology.\u003C/p>","\u003Cul>\r\n\u003Cli>Hot-Plug Specification\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003Cli>CompactPCI\u003C/li>\r\n\u003Cli>The 64-bit PCI Extension\u003C/li>\r\n\u003Cli>66 MHz PCI Implementation\u003C/li>\r\n\u003Cli>Expansion ROMs\u003C/li>\r\n\u003Cli>PCI-to-PCI Bridge and the PCI BIOS\u003C/li>\r\n\u003Cli>Add-in cards and connectors\u003C/li>\r\n\u003Cli>Bus arbitration\u003C/li>\r\n\u003Cli>Reduced-wave switching\u003C/li>\r\n\u003Cli>Early transaction end\u003C/li>\r\n\u003Cli>Fast back-to-back and stepping\u003C/li>\r\n\u003C/ul>","\u003Cp class=\"body\">\u003Cstrong>Tom Shanley\u003C/strong>, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.\u003C/p>\r\n\u003Cp class=\"body\">\u003Cstrong>Don Anderson\u003C/strong> has 29 year's combined development experience in analog and digital electronics and the computer industry, working for companies such as Hewlett Packard, Schlumberger, and Compaq. Since joining MindShare in 1991, he has authored and co-authored 12 books on PC Architecture and has taught over 500 courses.\u003C/p>","Tom Shanley, Don Anderson",833,[],[],"MindShare PCI book","pci, book, mindshare",[],{"id":239,"name":240,"slug":241,"category_id":7,"author":8,"revision":118,"errata_text":10,"errata_link":242,"price":8,"file_path":12,"file_name":243,"cover_url":244,"peek_inside_file":8,"peek_inside_url":8,"overview":245,"has_book":16,"book_out_of_stock":16,"key_topics":246,"about_the_authors":123,"info":145,"authors":125,"publisher":189,"pages":247,"retail_price":191,"ebook_price":94,"book_price":25,"combined_price":25,"tags":248,"price_type":30,"related_items":249,"shipping_details":8,"is_active":35,"meta_title":8,"meta_description":250,"meta_keywords":251,"user_ebook":252},371,"PCI-X System Architecture","pci-x-system-architecture","https://www.mindshare.com/images/PCI-X%20Errata.pdf","MindShare_PCI-X_eBook_v1.0.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/PCI-X_System_Architecture_cover-2025-06-30_15%3A10%3A23.jpg","\u003Cp>PCI-X is the successor to the Peripheral Component Interconnect (PCI) Bus Specification, the current standard that enables communication between peripheral devices and the computer processor. A major improvement over the older PCI technology, PCI-X enables significantly higher performance with transfer rates of up to 1.06 GB per second.\u003C/p>\r\n\u003Cp>PCI-X System Architecture is a detailed and comprehensive guide to the PCI-X technology. It highlights the many changes and improvements from PCI 2.2 to PCI-X so that you can build on your PCI knowledge to master PCI-X with greater ease. The book discusses the drawbacks of PCI and how PCI-X solves these problems, achieving faster transfer rates. In addition, it presents in-depth information and practical guidance on the PCI-X transaction protocol, device configuration for PCI-X, load tuning, PCI-X bridges, error detection and handling, and electrical issues. You will find specific information on such key topics as:\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>The CD-ROM includes a 70-minute PCI-X overview video by Tom Shanley, featuring an introduction to the basic concepts underlying PCI-X bus technology. Topics covered include terminology, detection of PCI-X-capable functions, the block-oriented bus, transaction types and phases, a detailed explanation of an example transaction, and how split transactions replace the delayed transactions of PCI.\u003C/p>\r\n\u003Cp>Anyone who designs or tests hardware or software that involves the PCI-X bus will find that PCI-X System Architecture is an essential resource for understanding and working with this important technology.\u003C/p>","\u003Cul>\r\n\u003Cli>Device types and bus initialization, including Hot-Plug PCI-X initialization\u003C/li>\r\n\u003Cli>Dword and burst commands\u003C/li>\r\n\u003Cli>Bus arbitration, latency rules, and burst transactions\u003C/li>\r\n\u003Cli>Transaction termination\u003C/li>\r\n\u003Cli>Split completion messages\u003C/li>\r\n\u003Cli>64-bit transactions\u003C/li>\r\n\u003Cli>Bridge and non-bridge configuration registers\u003C/li>\r\n\u003Cli>Load tuning, including adjustable fields and registers, split completion buffers, and adjusting timeslice values\u003C/li>\r\n\u003Cli>PCI-XtoPCI-X Bridges\u003C/li>\r\n\u003Cli>Handling master abort, attribute phase parity errors, and split read errors\u003C/li>\r\n\u003C/ul>",688,[],[],"MindShare PCI-X book","pci-x, book, mindshare",[],{"id":254,"name":255,"slug":256,"category_id":7,"author":8,"revision":118,"errata_text":8,"errata_link":8,"price":8,"file_path":12,"file_name":257,"cover_url":258,"peek_inside_file":8,"peek_inside_url":8,"overview":259,"has_book":16,"book_out_of_stock":16,"key_topics":260,"about_the_authors":261,"info":262,"authors":167,"publisher":189,"pages":263,"retail_price":264,"ebook_price":265,"book_price":25,"combined_price":25,"tags":266,"price_type":30,"related_items":267,"shipping_details":268,"is_active":35,"meta_title":8,"meta_description":270,"meta_keywords":271,"user_ebook":272},372,"FireWire System Architecture (2nd Edition)","firewire-system-architecture-2nd-edition","MindShare_Firewire_2nd_eBook_v1.0.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/FireWire_System_Architecture_%282nd_Edition%29_cover-2025-06-30_15%3A12%3A37.jpg","\u003Cp>MindShare's FireWire System Architecture provides an in-depth description of the IEEE 1394a cable environment, based on the 2.0 version of the 1394a standard. Comprehensive, concise, and well-organized, this book details the specification itself and presents the architecture, features, and operations of systems developed with the FireWire bus. Completely up-to-date, this new edition covers all of the changes incorporated into the 2.0 standard, such as arbitration enhancements, improvements in bus reset timing, new PHY register definition, and port interface enhancements to support suspend/resume and port disable. In addition, it provides in-depth information on suspend/resume operation, power distribution, and power management.\u003C/p>\r\n\u003Cp>FireWire System Architecture describes the various hardware and software layers that make up the FireWire serial bus and provides transaction examples to explain and illustrate the relationship between each layer.\u003C/p>","\u003Cul>\r\n\u003Cli>The communications model\u003C/li>\r\n\u003Cli>Asynchronous and isochronous transactions\u003C/li>\r\n\u003Cli>Cables and connectors\u003C/li>\r\n\u003Cli>The electrical interface\u003C/li>\r\n\u003Cli>Asynchronous and isochronous arbitration, including such enhancements as fly-by arbitration, acceleration control, and priority arbitration service\u003C/li>\r\n\u003Cli>Packets, including the PHY packet format\u003C/li>\r\n\u003Cli>Serial bus configuration and management\u003C/li>\r\n\u003Cli>Control and status registers (CSRs)\u003C/li>\r\n\u003Cli>Configuration ROM\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cspan style=\"font-weight: bold;\">Don Anderson\u003C/span> has 29 year's combined development experience in analog and digital electronics and the computer industry, working for companies such as Hewlett Packard, Schlumberger, and Compaq. Since joining MindShare in 1991, he has authored and co-authored 12 books on PC Architecture, and has taught over 500 courses.\u003C/p>","\u003Cp>\"Finally, a book on IEEE 1394 that's easy to understand!!! MindShare's \u003Cem>FireWire System Architecture: IEEE 1394\u003C/em> provides a consolidated learning tool for 1394 hardware and software, and confirms the statement, '1394's for the fun stuff....'\"\u003Cbr>     - Phil Roden, 1394 Digital Design Manager, Texas Instruments\u003C/p>",509,"54.99","15",[],[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":269},0.004,"MindShare FireWire book","firewire, 1394a, 1394b, book, mindshare",[],{"id":274,"name":275,"slug":276,"category_id":7,"author":8,"revision":118,"errata_text":8,"errata_link":8,"price":8,"file_path":12,"file_name":277,"cover_url":278,"peek_inside_file":8,"peek_inside_url":8,"overview":279,"has_book":16,"book_out_of_stock":16,"key_topics":280,"about_the_authors":281,"info":145,"authors":231,"publisher":189,"pages":282,"retail_price":283,"ebook_price":265,"book_price":25,"combined_price":25,"tags":284,"price_type":30,"related_items":285,"shipping_details":286,"is_active":35,"meta_title":8,"meta_description":287,"meta_keywords":288,"user_ebook":289},379,"ISA System Architecture (3rd Edition)","isa-system-architecture-3rd-edition","MindShare_ISA_3rd_eBook.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/ISA_System_Architecture_%283rd_Edition%29_cover-2025-06-30_15%3A21%3A13.jpg","\u003Cp>\u003Cem>\u003Cstrong>ISA System Architecture\u003C/strong>\u003C/em> describes the hardware architecture of ISA (Industry Standard Architecture), providing a clear, concise explanation of an ISA system in detail. This book is divided into three parts:\u003Cbr>\u003Cbr>\u003Cstrong>Part 1: The System Kernel\u003C/strong>\u003Cbr>This section provides a detailed tutorial on how Intel X86 microprocessors communicate with memory and I/O devices. Included is the support logic which allows the microprocessor to communicate with 8- and 16-bit devices and detailed descriptions of the signals and timing involved in all Bus Cycle types.\u003Cbr>\u003Cbr>\u003Cstrong>Part 2: Memory Subsystems\u003C/strong>\u003Cbr>The memory section provides a detailed theory of operation of RAM and ROM devices, along with implementations commonly used in ISA systems. The section also covers the concepts and terminology related to cache memory designs.\u003Cbr>\u003Cbr>\u003Cstrong>Part 3: The Industry Standard Architecture\u003C/strong>\u003Cbr>This section provides a detailed discussion of the ISA Bus Architecture including ISA bus cycles and timing, along with ISA implementations of Interrupts, DMA, Real-Time Clock and Configuration RAM, Numeric Coprocessors, Keyboard/Mouse Interface, and Timers.\u003C/p>","\u003Cul>\r\n\u003Cli>Bus cycles\u003C/li>\r\n\u003Cli>Addressing\u003C/li>\r\n\u003Cli>I/O\u003C/li>\r\n\u003Cli>RAM, ROM, and cache memory\u003C/li>\r\n\u003Cli>Cache architectures\u003C/li>\r\n\u003Cli>Decode and reset logic\u003C/li>\r\n\u003Cli>Interrupts\u003C/li>\r\n\u003Cli>System kernel\u003C/li>\r\n\u003Cli>Bus mastering\u003C/li>\r\n\u003Cli>DMA\u003C/li>\r\n\u003Cli>RTC and configuration RAM\u003C/li>\r\n\u003C/ul>","\u003Cp>Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.\u003C/p>\r\n\u003Cp>Don Anderson has over 30 years of experience in the technical electronics and computer industry. He has authored 14 books covering various aspects of computer hardware and system design. Topics include system architectures, parallel bus technologies, serial bus technologies, and processor architectures. Don has trained thousands of engineers in the US and around the world. Before joining MindShare, Don worked for Compaq, Schlumberger, Geosource and Hewlett Packard.\u003C/p>",517,"49.99",[],[],{"book_width":33,"book_length":33,"book_height":33,"book_weight":34},"MindShare ISA System Architecture book","mindshare, isa, book, ebook",[],1793031956167]