Each CPU and chipset generation brings new capabilities while maintaining backward compatibility with earlier platforms. New 9th and 10th generation CPU architectures offer significant improvements in instruction throughput, power conservation, integrated graphics, security, system-on-a-chip (SOC) packaging options, etc. This 5-day course introduces the x86 Instruction Set Architecture (ISA) and describes the hardware features of the latest Intel Core and Xeon CPUs supporting it. In addition, the course presents an overview of memory, platform controller hub (PCH) logic, and IO interfaces that may be employed when implementing common system types.

A full understanding of an Intel x86 hardware platform includes knowledge of CPU/PCH capabilities, BIOS/OS setup of programmable platform features, as well as the dynamic status of the system with regards to thermal and error events, etc. MindShare Arbor demonstrations integrated into this course present a decoded view of register setup, system and device status, as well as a coherent summary of platform information reported when the CPUID instruction is executed. Students may use Arbor software for real-time scans of local systems, read/modify specific registers, and even save Arbor scan results for later sharing and off-line review.

This course is updated as frequently as possible in an attempt to provide a “snapshot” of Intel Core and Xeon x86 platform components and system implementations. Content is based on publicly available documents.