[{"data":1,"prerenderedAt":1187},["ShallowReactive",2],{"GET-course-category/all?search=-{}-{}":3,"GET-elearning-course/all-{}-{}":37,"GET-elearning-course/slug/pc-virtualization-elearning-course-{}-{}":443,"GET-business-site/grouped-courses-by-category-{}-{}":818},[4,8,12,15,18,22,26,29,33],{"id":5,"title":6,"order":7},147,"PCI Express Courses",0,{"id":9,"title":10,"order":11},2,"CXL Courses",1,{"id":13,"title":14,"order":9},3,"USB Courses",{"id":16,"title":17,"order":13},22,"Memory Courses",{"id":19,"title":20,"order":21},17,"Virtualization Courses",4,{"id":23,"title":24,"order":25},18,"Storage Courses",5,{"id":25,"title":27,"order":28},"ARM Courses",6,{"id":30,"title":31,"order":32},148,"x86 Architecture Courses",7,{"id":34,"title":35,"order":36},149,"Firmware Courses",8,{"data":38},[39,56,69,82,94,105,115,125,135,145,155,166,174,182,192,204,215,223,233,242,252,260,269,279,288,297,305,314,321,329,337,346,354,363,373,383,392,401,409,417,426,434],{"id":40,"name":41,"about":42,"description":43,"slug":44,"instructor_fullname":45,"instructor_email":46,"equivelent_of":47,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":19,"you_will_learn":50,"prerequisites":51,"is_active":52,"modified_at":53,"presentation_id":54,"release_date":55},1744,"IO Virtualization for Intel Platforms eLearning Course","\u003Cp>Let MindShare Bring \"IO Virtualization\" to Life for You\u003C/p>","\u003Cp>Virtualization is one of the hot, exciting areas in the industry today, generating significant revenue, and solving critical problems in data centers and in embedded and mobile markets. However, software virtualization techniques add too much overhead to allow virtualization to be used for some applications. This class will look at those problem applications and the hardware solutions architected by Intel as well as support in standards like PCI Express (PCIe). The course focuses on the Intel processor SoC or Chipset VT-d elements that support DMA and Interrupt remapping. The course also discusses details of Address Translation Services (ATS), Access Control Services (ACS) and Single-Root IOV (SRIOV) implementations. This course has been updated to cover Intel's Scalabale IOV technology as well.\u003C/p>","io-virtualization-for-intel-platforms-elearning-course","Joe Winkles","joe@mindshare.com",90,120,"995","\u003Cul>\r\n\u003Cli>What virtualization is, and the revenue generating uses for virtualization\u003C/li>\r\n\u003Cli>The major sources of overhead with software-only virtualization techniques\u003C/li>\r\n\u003Cli>How I/O virtualization will use the new hardware assists, to solve these problems\u003C/li>\r\n\u003Cli>Intel architecture focused VT-d (multiple generations)\u003C/li>\r\n\u003Cli>DMA remapping (Guest Physical to Host Physical as well as Shared Virtual Memory)\u003C/li>\r\n\u003Cli>PCIe Address Translation Services (ATS)\u003C/li>\r\n\u003Cli>PCIe Access Control Services (ACS)\u003C/li>\r\n\u003Cli>Single Root IOV (SRIOV)\u003C/li>\r\n\u003Cli>Shared Virtual Memory (SVM)\u003C/li>\r\n\u003Cli>Process Address Space IDs (PASIDs)\u003C/li>\r\n\u003Cli>Scalable IO Virtualization\u003C/li>\r\n\u003Cli>Posted Interrupts\u003C/li>\r\n\u003C/ul>","\u003Cp>None\u003C/p>",true,"2025-08-06 14:27:13",484,"11/15/24",{"id":57,"name":58,"about":59,"description":60,"slug":61,"instructor_fullname":62,"instructor_email":63,"equivelent_of":11,"subscription_length":48,"price":64,"price_arbor":64,"course_category_id":13,"you_will_learn":65,"prerequisites":66,"is_active":52,"modified_at":67,"presentation_id":68,"release_date":55},1719,"xHCI eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"xHCI\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>This one-day course targets software/hardware engineers and others requiring an introduction to Intel’s xHCI USB host controller model. A popular training combination is the three-day Comprehensive USB 3.1 course followed by this one-day xHCI Fundamentals course. Note that MindShare also offers a two-day xHCI course for those needing additional details on the xHCI host controller and software management of registers and memory data structures.\u003C/p>","xhci-elearning-course","Jay Trodden","eLearning@mindshare.com","395","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Details regarding the implementation and operation of the eXtensible Host Controller Interface (xHCI)\u003C/li>\r\n\u003Cli>How to initialize and configure an xHC for runtime operation\u003C/li>\r\n\u003Cli>The behavior and purpose of all the data structures (PCI config space, MMIO space and system memory structures) associated with an xHC including how to explore them on a live running system\u003C/li>\r\n\u003Cli>The events that occur during an attach and remove event\u003C/li>\r\n\u003Cli>And much more\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>A good understanding of SuperSpeed (USB 3.x) protocol.\u003C/p>",null,406,{"id":70,"name":71,"about":72,"description":73,"slug":74,"instructor_fullname":75,"instructor_email":76,"equivelent_of":13,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":5,"you_will_learn":77,"prerequisites":78,"is_active":52,"modified_at":79,"presentation_id":80,"release_date":81},1755,"Core PCIe eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PCIe\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>If you are going to take one course on PCI Express, this should be it. MindShare's PCIe eLearning course is an exhaustive tutorial on PCIe from the electrical PHY all the way up to software. It starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.\u003C/p>","core-pcie-elearning-course","Mike Jackson","mike@mindshare.com","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>PCI Express features and capabilities\u003C/li>\r\n\u003Cli>The definition and responsibilities of each of the layers in the interface\u003C/li>\r\n\u003Cli>How hardware-based automatic error detection and correction mechanism works\u003C/li>\r\n\u003Cli>The various additional levels of error detection and reporting\u003C/li>\r\n\u003Cli>The details of the packet-based protocol used by PCIe\u003C/li>\r\n\u003Cli>The address space and packet-routing methods used\u003C/li>\r\n\u003Cli>How the various power management techniques work\u003C/li>\r\n\u003Cli>Configuration register details that provide control and status visibility to software\u003C/li>\r\n\u003Cli>The purpose of equalization and how it is done in PCIe 3.0 and later\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>None.\u003C/p>","2026-10-22 16:26:43",502,"11/16/24",{"id":83,"name":84,"about":85,"description":86,"slug":87,"instructor_fullname":88,"instructor_email":89,"equivelent_of":11,"subscription_length":48,"price":90,"price_arbor":90,"course_category_id":9,"you_will_learn":91,"prerequisites":51,"is_active":52,"modified_at":92,"presentation_id":93,"release_date":55},1756,"CXL Fundamentals eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"CXL\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare’s CXL Fundamentals course provides a solid foundation of platform architectures and use cases of the three CXL protocols with Type 1, Type 2 and Type 3 devices. Engineering managers will learn about features and capability of each of the three device types allowing decision making about which type of device to implement.    \u003C/p>","cxl-fundamentals-elearning-course","Ravi Budruk","ravi@mindshare.com","595","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>CXL system architectures with Type 1, Type 2 and Type 3 devices\u003C/li>\r\n\u003Cli>CXL Port Layers with an overview of each\u003C/li>\r\n\u003Cli>Intro to DVSEC and Component Register Space for CXL\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","2025-07-24 18:56:26",503,{"id":95,"name":96,"about":97,"description":98,"slug":99,"instructor_fullname":88,"instructor_email":89,"equivelent_of":25,"subscription_length":48,"price":100,"price_arbor":100,"course_category_id":9,"you_will_learn":101,"prerequisites":102,"is_active":52,"modified_at":103,"presentation_id":104,"release_date":55},1758,"CXL 2.0 eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"CXL 2.0\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare’s comprehensive CXL 2.0 Architecture course provides a solid foundation of platform architectures and use cases of the three CXL protocols with Type 1, Type 2 and Type 3 devices in platform example. The course details the role of the Transaction Layer protocol, Link Layer including Flit packing and unpacking, ARB/MUX and Flex Bus Logical and Electrical Physical Layer of a CXL port design. We explain enumeration and configuration process during system bring-up with details of configuration and component registers. Other topics include switch architecture, reset, manageability, RAS features, power management, performance considerations and compliance testing.\u003C/p>","comprehensive-cxl-20-elearning-course","1595","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>CXL system architectures with Type 1, Type 2 and Type 3 devices\u003C/li>\r\n\u003Cli>CXL transaction protocol for CXL.io and CXL.cache/mem\u003C/li>\r\n\u003Cli>CXL port design constituting Transaction, Link, ARB/MUX and Flex Bus Physical Layers\u003C/li>\r\n\u003Cli>CXL switch architecture (optional)\u003C/li>\r\n\u003Cli>Enumeration and initialization issues with configuration register definitions\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003Cli>Reliability, Availability, Serviceability (RAS) and error handling features\u003C/li>\r\n\u003Cli>Considerations to improve protocol performance\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>PCIe 5.0 knowledge is recommended.\u003C/p>","2025-01-01 23:28:14",505,{"id":106,"name":107,"about":108,"description":109,"slug":110,"instructor_fullname":75,"instructor_email":76,"equivelent_of":13,"subscription_length":48,"price":111,"price_arbor":111,"course_category_id":23,"you_will_learn":112,"prerequisites":78,"is_active":52,"modified_at":67,"presentation_id":113,"release_date":114},1736,"SAS 3.0 Storage Technology eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"SAS 3.0\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare’s SAS Architecture course provides a comprehensive understanding of the Serial Attached SCSI interface. The course covers all aspects of the standard, primarily from a hardware perspective, and compares the usage model of SAS with other enterprise interface designs. Practical examples of the discovery process, transactions on the link, and error conditions help provide a great introduction for those new to this material. MindShare’s established background in legacy platform design, coupled with a comprehensive understanding of the latest bus technologies, provides rich insight into the SAS design and results in a superior training experience. This course will provide the kind of in-depth information, example implementations, and practical guidance that will give your team a running start on working with SAS.\u003C/p>","sas-30-storage-technology-elearning-course","695","\u003Cul>\r\n\u003Cli>The basics of the serial interface\u003C/li>\r\n\u003Cli>System topology considerations\u003C/li>\r\n\u003Cli>How connections are built and handled\u003C/li>\r\n\u003Cli>How the SAS infrastructure handles different protocols\u003C/li>\r\n\u003Cli>The responsibilities of each design layer\u003C/li>\r\n\u003Cli>How problems are reported and handled\u003C/li>\r\n\u003Cli>The changes made to SAS 3.0\u003C/li>\r\n\u003C/ul>",463,"11/14/24",{"id":116,"name":117,"about":118,"description":119,"slug":120,"instructor_fullname":88,"instructor_email":89,"equivelent_of":13,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":9,"you_will_learn":121,"prerequisites":122,"is_active":52,"modified_at":123,"presentation_id":124,"release_date":55},1763,"CXL 3.1 Update eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"CXL 3.1\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>This course is meant to go through all the new and updated topics introduced in the CXL 3.0 and 3.1 specs. This course does expect the learner to already have a solid understanding of CXL 2.0.\u003C/p>","cxl-31-update-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>256 Byte Flit Mode\u003C/li>\r\n\u003Cli>Port-Based Routing\u003C/li>\r\n\u003Cli>Cache.mem Back-Invalidations\u003C/li>\r\n\u003Cli>CXL Fabric extensions\u003C/li>\r\n\u003Cli>and much more...\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>CXL 2.0 knowledge is required.\u003C/p>","2025-07-15 19:02:55",521,{"id":126,"name":127,"about":128,"description":129,"slug":130,"instructor_fullname":131,"instructor_email":63,"equivelent_of":11,"subscription_length":48,"price":64,"price_arbor":64,"course_category_id":23,"you_will_learn":132,"prerequisites":133,"is_active":52,"modified_at":67,"presentation_id":134,"release_date":114},1745,"Advanced Host Controller Interface (AHCI) eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"AHCI\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>This course provides details of the behavior and registers involved with the Advanced Host Controller Interface (AHCI) used by SATA devices.\u003C/p>","advanced-host-controller-interface-ahci-elearning-course","Don Anderson","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Details regarding the implementation and operation of the Advanced Host Controller Interface (AHCI)\u003C/li>\r\n\u003Cli>The sequence of events associated with AHCI initialization, including PCIe Configuration, BIOS and the AHCI driver\u003C/li>\r\n\u003Cli>How to validate the Command List and Command Table entries and operation, using MindShare's Arbor Tool\u003C/li>\r\n\u003Cli>How to verify proper Native Command Queuing protocol, using MindShare's Arbor tool\u003C/li>\r\n\u003Cli>Details associated with the AHCI Register Block, including field definition and usage\u003C/li>\r\n\u003Cli>The details associated with the Port Registers, including field definition and usage\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>An understanding of SATA protocol.\u003C/p>",405,{"id":136,"name":137,"about":138,"description":139,"slug":140,"instructor_fullname":75,"instructor_email":76,"equivelent_of":11,"subscription_length":48,"price":141,"price_arbor":141,"course_category_id":5,"you_will_learn":142,"prerequisites":78,"is_active":52,"modified_at":143,"presentation_id":144,"release_date":55},1710,"Fundamentals of PCI Express eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PCIe\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>This course provides a good overview of the basics of PCIe. This course is meant for people who want a general understanding of the PCIe architecture, but don't need to dive into the details.\u003C/p>","fundamentals-of-pci-express-elearning-course","495","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Short background of PCI concepts important to PCIe\u003C/li>\r\n\u003Cli>Motivation for PCIe serial model\u003C/li>\r\n\u003Cli>Software view of the topology\u003C/li>\r\n\u003Cli>Definition and responsibilities of each layer in the PCIe interface\u003C/li>\r\n\u003Cli>PCIe transaction types and definitions\u003C/li>\r\n\u003Cli>The routing method used for each request and completion\u003C/li>\r\n\u003Cli>Roles of the Flow Control and ACK / NAK features\u003C/li>\r\n\u003Cli>Purpose and behavior of the logical blocks within the Physical Layer\u003C/li>\r\n\u003Cli>Error types and the associated levels of severity\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","2025-07-17 17:05:46",272,{"id":146,"name":147,"about":138,"description":148,"slug":149,"instructor_fullname":45,"instructor_email":46,"equivelent_of":13,"subscription_length":48,"price":150,"price_arbor":150,"course_category_id":5,"you_will_learn":151,"prerequisites":152,"is_active":52,"modified_at":153,"presentation_id":154,"release_date":114},1750,"Advanced PCIe eLearning Course","\u003Cp> \u003Cspan style=\"color: rgb(108, 108, 108); font-size: 18px; font-weight: bold;\">Advanced PCI Express 3.x, 4.0 & 5.0 (w/ PIPE) eLearning Course Info\u003C/span>\u003C/p>\r\n\u003Cp> \u003Cspan style=\"color: rgb(255, 10, 10); font-size: 16px; font-weight: bold;\">Note: This course is a subset of the Comprehensive PCIe 5.0 eLearning course.\u003C/span>\u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(255, 10, 10); font-size: 16px; font-weight: bold;\"> Note: Purchase of this course includes the PIPE 6.0 eLearning course.\u003C/span>\u003C/p>\r\n\u003Cp>If you already understand PCIe protocol as described in the rev 2.0 specification and you need to understand spec additions from spec rev 3.0 onwards, this is the course to take. To serve as a refresher, the course starts with a high-level view of the design to provide the big-picture context. The course then drills down into design updates associated with Gen3, Gen4 and Gen5. We cover topics such as 128b/130b, Retimers, Lane Margining etc.\u003C/p>","advanced-pcie-elearning-course","895","\u003Cul>\r\n\u003Cli>PCI Express features and capabilities\u003C/li>\r\n\u003Cli>The definition and responsibilities of each of the layers in the interface\u003C/li>\r\n\u003Cli>Physical Layer changes to support PCIe Gen3, Gen4 and Gen5 such as 128b/130b and Tx Equalization\u003C/li>\r\n\u003Cli>The link training process including changes made in rev 5.0 spec such as Alternate Protocol Negotiation\u003C/li>\r\n\u003Cli>The purpose of equalization and how it is done in PCIe 3.0 and later\u003C/li>\r\n\u003Cli>Features added to Rev 4.0 and Rev 5.0 spec such as Lane Margining, Retimers, System Firmware Intermediary\u003C/li>\r\n\u003C/ul>","\u003Cp>A solid understanding of PCIe 2.x is needed since this course only covers the deltas between 2.x and 5.0.\u003C/p>","2025-07-23 16:27:39",490,{"id":156,"name":157,"about":158,"description":159,"slug":160,"instructor_fullname":161,"instructor_email":162,"equivelent_of":21,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":34,"you_will_learn":163,"prerequisites":164,"is_active":52,"modified_at":67,"presentation_id":165,"release_date":114},1747,"UEFI x64 Architecture eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"UEFI\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>This course will give you a thorough understanding of how x86 UEFI firmware takes control of the system and prepares to hand control to an OS boot loader, starting from the reset vector. On the first day of training, we will give you a quick overview of legacy BIOS (and its inherent limitations) and review how UEFI and its architecture addresses legacy BIOS shortcomings.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>The other two days are dedicated to walking and working through the UEFI Forum's PI (Platform Initialization) spec's seven phases and explain how modules are discovered and dependencies are resolved as system hardware is initialized. We will wrap up with Secure Boot to get a better idea about Microsoft's boot requirements.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>This course is designed to be hands-on, allowing you to experiment with code that you will write to get a better handle on the various PI phases. At the end of the course, you will be able to write a DXE driver for a simple hardware device. You will also be able to write UEFI applications that run at the UEFI shell.\u003C/p>","uefi-x64-architecture-elearning-course","Paul Devriendt","paul@mindshare.com","\u003Cul>\r\n\u003Cli>The order and relevance of UEFI PI/Tiano's phases.\u003C/li>\r\n\u003Cli>When and *how* key subsystems and devices are detected, initialized, and configured.\u003C/li>\r\n\u003Cli>How to leverage Platform Configuration Database to simplify the coding process.\u003C/li>\r\n\u003Cli>How to write a PEI or DXE device driver.\u003C/li>\r\n\u003Cli>How to effectively debug PEI and DXE PI phases.\u003C/li>\r\n\u003Cli>Where device configuration and management information is collected, stored, and communicated between the phases and to an operating system, including ACPI info.\u003C/li>\r\n\u003Cli>Process of handing over system control from Firmware to OS.\u003C/li>\r\n\u003C/ul>","\u003Cp>Attendees are expected to have a technical background. Basic knowledge of assembly language programming, microprocessor technology, memory, and standard peripherals is expected.\u003C/p>",489,{"id":167,"name":168,"about":169,"description":170,"slug":171,"instructor_fullname":161,"instructor_email":162,"equivelent_of":13,"subscription_length":48,"price":150,"price_arbor":150,"course_category_id":25,"you_will_learn":172,"prerequisites":51,"is_active":52,"modified_at":67,"presentation_id":173,"release_date":114},1743,"ARMv8-M and v8.1-M eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARMv8-M\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>This course is aimed at software developers and system architects developing for systems powered by ARMv8-M processors, such as the Cortex-M23 and the Cortex-M33 processors. It is relevant for operating system development, device driver development, low-level coding and security firmware, and for validation and debug.\u003C/p>","armv8-m-and-v81-m-elearning-course","\u003Cul>\r\n\u003Cli>ARM’s v8-M architecture.\u003C/li>\r\n\u003Cli>The relationship to other ARM architectures.\u003C/li>\r\n\u003Cli>The changes from the earlier v6-M and v7-M architectures.\u003C/li>\r\n\u003Cli>The optional FPU and DSP extensions.\u003C/li>\r\n\u003Cli>Platform and tools overview.\u003C/li>\r\n\u003C/ul>",482,{"id":175,"name":176,"about":177,"description":178,"slug":179,"instructor_fullname":75,"instructor_email":76,"equivelent_of":11,"subscription_length":48,"price":64,"price_arbor":64,"course_category_id":5,"you_will_learn":180,"prerequisites":181,"is_active":52,"modified_at":67,"presentation_id":154,"release_date":55},1748,"PIPE 6.0 - PHY Interface for PCI Express and more","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PIPE 6.0\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>PIPE 6.0 enables the development of PHYs for PCI Express, SATA, USB, DisplayPort, and USB4. Such PIPE compliant PHYs can be delivered as standalone ICs or as macrocell IPs for inclusion in ASICs. The course describes a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. Two independently designed PHY and MAC ASICs/macrocell IPs will connect and work together as long as they meet the design requirements of PIPE 6.0. This course does not describe the internal design of a compliant PHY chip or higher layer protocol architecture. To understand PCIe, SATA or USB architecture, you would need to take one of MindShare’s other comprehensive architecture courses.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>The course covers PIPE interface operational behavior in PCIe, USB and SATA modes. Additionally, you will also learn the signaling protocol associated with the Link Training process, Equalization process and Lane Margining.\u003C/p>","pipe-60-phy-interface-for-pci-express-and-more","\u003Cul>\r\n\u003Cli>Signals and protocol associated with communication between the MAC layer (of PCIe, SATA, USB 3.1, USB4 and DisplayPort) and PHY layer\u003C/li>\r\n\u003Cli>Register definitions both in the MAC and PHY layers\u003C/li>\r\n\u003Cli>Signaling to support the PHY equalization process\u003C/li>\r\n\u003Cli>PCIe power state support\u003C/li>\r\n\u003Cli>USB and SATA operational modes\u003C/li>\r\n\u003C/ul>","\u003Cp>A basic understanding of PCI Express, SATA, USB 3.1/USB4 and DisplayPort protocols which serves as a\u003Cbr>basis to understanding the packets and signals that traverse the PIPE interface.\u003C/p>",{"id":183,"name":184,"about":185,"description":186,"slug":187,"instructor_fullname":75,"instructor_email":76,"equivelent_of":21,"subscription_length":48,"price":100,"price_arbor":188,"course_category_id":23,"you_will_learn":189,"prerequisites":51,"is_active":52,"modified_at":190,"presentation_id":67,"release_date":191},1813,"UFS 4.0 eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"UFS 4.0\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare's Universal Flash Storage (UFS) course begins with a high-level view of the architecture that provides the big-picture context of the hardware architecture and software interactions. Then, we drill down into details for each aspect of the UFS architecture. \u003C/p>","ufs4-elearning-course","0","\u003Cul>\r\n\u003Cli>UFS model and design goals\u003C/li>\r\n\u003Cli>Definition and functionality of the design layers\u003C/li>\r\n\u003Cli>Overview of the software stack\u003C/li>\r\n\u003Cli>Basics of the UFS Host Controller Interface model\r\n\u003Cul>\r\n\u003Cli>Device initialization\u003C/li>\r\n\u003Cli>How command queues are set up and managed\u003C/li>\r\n\u003Cli>How software Informs the controller of new commands and learns when commands have been completed\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Extended features defined\u003C/li>\r\n\u003Cli>Error reporting structures defined\u003C/li>\r\n\u003Cli>Definition and functionality of the physical interface to the system\r\n\u003Cul>\r\n\u003Cli>UniPro\u003C/li>\r\n\u003Cli>M-PHY\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Power management options for the device and the UniPro interface\u003C/li>\r\n\u003C/ul>","2025-07-31 19:13:31","07/01/25",{"id":193,"name":194,"about":195,"description":196,"slug":197,"instructor_fullname":198,"instructor_email":199,"equivelent_of":21,"subscription_length":48,"price":100,"price_arbor":100,"course_category_id":16,"you_will_learn":200,"prerequisites":51,"is_active":52,"modified_at":201,"presentation_id":202,"release_date":203},1757,"Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4) eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"DRAM\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>This course is hardware-centric and also describes initialization and training of DRAM devices and controllers. It is suitable for hardware engineers and software/firmware engineers will also benefit. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers. This course introduces current DRAM technologies, concentrating on DDR4 as a baseline to teach concepts that are common to all DRAMs. The course then continues to cover in detail all new features of DDR5, DDR4, LPDDR5, and LPDDR4.\u003C/p>","modern-dram-ddr5-ddr4-lpddr5-lpddr4-elearning-course","John Swindle","john.swindle@mindshare.com","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Where JEDEC expects DRAM to appear in a system\u003C/li>\r\n\u003Cli>How a DRAM cell is addressed by the controller\u003C/li>\r\n\u003Cli>Difference between Banks, Bank Groups and Ranks\u003C/li>\r\n\u003Cli>Why the DRAM controller is so complicated\u003C/li>\r\n\u003Cli>Activation, Precharge and Refresh\u003C/li>\r\n\u003Cli>DDR4 pin definitions\u003C/li>\r\n\u003Cli>DDR4 bank state diagram\u003C/li>\r\n\u003Cli>DDR4 timing waveforms\u003C/li>\r\n\u003Cli>Prefetch Width\u003C/li>\r\n\u003Cli>Types of DIMMs\u003C/li>\r\n\u003Cli>Fly-By Routing\u003C/li>\r\n\u003Cli>PC and LP DRAM device architectures and features including DDR5 and LPDDR5\u003C/li>\r\n\u003Cli>DDR5/LPDDR4/LPDDR5 pin definitions\u003C/li>\r\n\u003Cli>DDR5/LPDDR4/LPDDR5 bank state diagrams\u003C/li>\r\n\u003Cli>DDR5/LPDDR4/LPDDR5 timing waveforms\u003C/li>\r\n\u003Cli>DDR5 DIMM PMIC\u003C/li>\r\n\u003Cli>Intro to NVDIMM\u003C/li>\r\n\u003Cli>Newer forms of Refresh\u003C/li>\r\n\u003Cli>POD and LVSTL signaling\u003C/li>\r\n\u003Cli>Clock throttling and dynamic voltage changes\u003C/li>\r\n\u003Cli>On-Die Termination (ODT)\u003C/li>\r\n\u003Cli>JEDEC Initialization and Mode Registers\u003C/li>\r\n\u003Cli>Calibration and training, including\r\n\u003Cul>\r\n\u003Cli>Vref training\u003C/li>\r\n\u003Cli>Read and Write calibration\u003C/li>\r\n\u003Cli>Write Leveling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Sources of errors and JEDEC features for handling errors\u003C/li>\r\n\u003Cli>Test philosophy and JEDEC features to assist with testing\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","2025-02-17 15:43:28",504,"09/03/22",{"id":205,"name":206,"about":207,"description":208,"slug":209,"instructor_fullname":45,"instructor_email":46,"equivelent_of":13,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":5,"you_will_learn":210,"prerequisites":211,"is_active":52,"modified_at":212,"presentation_id":213,"release_date":214},1761,"PCIe6 Update eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PCIe6\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cdiv>This course is perfect for someone with a good understanding of PCIe 5.0, but is wanting to quickly understand the massive number of changes introduced in the PCIe 6.0 specification.\u003C/div>","pcie6-update-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>PAM4 signaling\u003C/li>\r\n\u003Cli>The need for Forward Error Correction\u003C/li>\r\n\u003Cli>Behavior of the Physical Layer at 64GT/s\u003C/li>\r\n\u003Cli>Flit format\u003C/li>\r\n\u003Cli>Ack/Nak protocol at the Flit level\u003C/li>\r\n\u003Cli>Shared vs Dedicated Flow Control Buffers\u003C/li>\r\n\u003Cli>TLP Format while in Flit Mode\u003C/li>\r\n\u003Cli>The need for Segments in some TLPs\u003C/li>\r\n\u003Cli>Benefits and operation of L0p\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>A good understanding of PCIe 5.x is a requirement for this course since it only covers the new and different features introduced with PCIe6.\u003C/p>","2025-04-03 20:50:51",515,"10/05/23",{"id":216,"name":217,"about":195,"description":218,"slug":219,"instructor_fullname":198,"instructor_email":199,"equivelent_of":11,"subscription_length":48,"price":90,"price_arbor":90,"course_category_id":16,"you_will_learn":220,"prerequisites":78,"is_active":52,"modified_at":221,"presentation_id":222,"release_date":114},1760,"Fundamentals of DRAM eLearning Course","\u003Cp>\u003Cstrong>Note: This course is a subset of the comprehensive course entitled: Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4) eLearning Course\u003C/strong>.\u003C/p>\r\n\u003Cp>If you purchase this fundamentals course and then want to upgrade to the comprehensive course, you will only have to pay the difference for the upgrade.\u003C/p>","fundamentals-of-dram","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Where JEDEC expects DRAM to appear in a system\u003C/li>\r\n\u003Cli>How a DRAM cell is addressed by the controller\u003C/li>\r\n\u003Cli>Difference between Banks, Bank Groups and Ranks\u003C/li>\r\n\u003Cli>Why the DRAM controller is so complicated\u003C/li>\r\n\u003Cli>Activation, Precharge and Refresh\u003C/li>\r\n\u003Cli>DDR4 pin definitions\u003C/li>\r\n\u003Cli>DDR4 bank state diagram\u003C/li>\r\n\u003Cli>DDR4 timing waveforms\u003C/li>\r\n\u003Cli>Prefetch Width\u003C/li>\r\n\u003Cli>Types of DIMMS\u003C/li>\r\n\u003Cli>Fly-By Routing\u003C/li>\r\n\u003Cli>PC and LP DRAM device architectures and features including DDR5 and LPDDR5\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","2025-08-11 21:03:00",508,{"id":224,"name":225,"about":226,"description":227,"slug":228,"instructor_fullname":229,"instructor_email":230,"equivelent_of":13,"subscription_length":48,"price":150,"price_arbor":150,"course_category_id":13,"you_will_learn":231,"prerequisites":78,"is_active":52,"modified_at":67,"presentation_id":232,"release_date":55},1737,"USB 3.1 eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"USB 3.1\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>This in-depth course is designed with the hardware or software engineer in mind. The course contains practical examples of USB 3.1 transactions and error conditions. It describes the rules required for a host and device to be specification compliant.\u003C/p>","comprehensive-usb-31-elearning-course","Pamela Frinzi","elearning@mindshare.com","\u003Cul>\r\n\u003Cli>USB 3.1 protocol\u003C/li>\r\n\u003C/ul>",467,{"id":234,"name":235,"about":236,"description":237,"slug":238,"instructor_fullname":161,"instructor_email":162,"equivelent_of":13,"subscription_length":48,"price":111,"price_arbor":111,"course_category_id":25,"you_will_learn":239,"prerequisites":240,"is_active":52,"modified_at":67,"presentation_id":241,"release_date":114},1715,"ARM MCU Architecture eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARM MCU\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>\u003Cspan class=\"sectionsubhead\">ARM Endorsement:\u003C/span>\u003C/p>\r\n\u003Cp style=\"padding-left: 40px;\">\u003Cem>“On the strength of MindShare’s position as an industry leader in technology training, particularly in the area of microprocessor architecture, we were happy to welcome them to the AAE program as an ARM Accreditation Training Partner (AATP). Their expertise in delivering engaging self-paced eLearning courses should make MindShare's ARM Accredited Engineer Certification eLearning course a very good way to efficiently and cost-effectively prepare for the ARM Accredited Engineer (AAE) exam”.\u003C/em>\u003Cbr>\u003Cstrong>- Daniel Dearing, AAE Program Manager\u003C/strong>\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>This was the only eLearning course endorsed by ARM for anyone wanting to take the ARM MCU Certification exam when ARM was still offering their AAME certification program (AAME - ARM Approved MCU Engineer). That program has been discontinued by ARM, but the information in this course is still very relevant and extremely valuable for anyone working with ARM microcontrollers.\u003C/p>","arm-mcu-architecture-elearning-course","\u003Cul>\r\n\u003Cli>ARM processor architecture (M0/M0+/M3/M4)\u003C/li>\r\n\u003Cli>ARM architecture v6-M/v7-M registers\u003C/li>\r\n\u003Cli>ARM instructions, syntax and assembly language programming\u003C/li>\r\n\u003Cli>Interrupt handling environment\u003C/li>\r\n\u003Cli>v6-M/v7-M memory model and protection\u003C/li>\r\n\u003Cli>Embedded software development and C/C++ compiler hints\u003C/li>\r\n\u003Cli>Cortex-M test and debug\u003C/li>\r\n\u003C/ul>","null",382,{"id":243,"name":244,"about":245,"description":246,"slug":247,"instructor_fullname":198,"instructor_email":199,"equivelent_of":21,"subscription_length":48,"price":100,"price_arbor":188,"course_category_id":16,"you_will_learn":248,"prerequisites":249,"is_active":52,"modified_at":250,"presentation_id":67,"release_date":251},1814,"HBM4E eLearning Course","\u003Cp>\u003Cstrong>\u003Cspan style=\"font-size: 18pt;\">Let MindShare Bring \"HBM4E\" to Life for You\u003C/span>\u003C/strong>\u003C/p>","\u003Cp>High Bandwidth Memory (HBM) is a form of DRAM used on the most capable HPC and SoC platforms. HBM is an evolution of WideIO and WideIO2 with some concepts borrowed from Graphics DRAM. HBM provides the maximum possible bandwidth of any DRAM technology, largely by implementing several very wide channels. All DRAM (PC DRAM, LP DRAM, Graphics DRAM, HBM) are very similar to one another, but there are significant differences in HBM that this course covers in detail up to and including HBM4E.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Ch3>\u003Cstrong>Course Topics:\u003C/strong>\u003C/h3>\r\n\u003Cul>\r\n\u003Cli>\u003Cstrong>Fundamentals of DRAM eLearning Course (included)\u003C/strong>\r\n\u003Cul>\r\n\u003Cli>System Architecture and Intro to DRAM\u003C/li>\r\n\u003Cli>DRAM Device Architecture\u003C/li>\r\n\u003Cli>Packaging and HBM\u003C/li>\r\n\u003Cli>DRAM Controller Basics and Addresses\u003C/li>\r\n\u003Cli>DDR4 Device and Pin Descriptions\u003C/li>\r\n\u003Cli>Signal Routing\u003C/li>\r\n\u003Cli>DDR4 - Bank State Machines, Commands and Waveforms\u003C/li>\r\n\u003Cli>Refresh\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>\u003Cstrong>HBM eLearning Course\u003C/strong>\r\n\u003Cul>\r\n\u003Cli>System Architecture and Packaging\r\n\u003Cul>\r\n\u003Cli>Example Platforms\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Channel Architecture, Device Organization and Device Architecture\r\n\u003Cul>\r\n\u003Cli>Features and Architectures of Previous Technologies (PC and LP DRAMs)\u003C/li>\r\n\u003Cli>HBM Channels and Pseudo channels\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Signal Descriptions\r\n\u003Cul>\r\n\u003Cli>Channel Signals\u003C/li>\r\n\u003Cli>Global Signals\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Bank State Machines, Commands and Waveforms\r\n\u003Cul>\r\n\u003Cli>Simultaneous Row and Column Commands\u003C/li>\r\n\u003Cli>Use of WDQS and RDQS\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Refresh\r\n\u003Cul>\r\n\u003Cli>Auto Refresh\u003C/li>\r\n\u003Cli>Self Refresh\u003C/li>\r\n\u003Cli>Single-bank (Per-bank) Refresh\u003C/li>\r\n\u003Cli>Row Hammer, Target Row Refresh and Refresh Management\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Electrical Specifications\r\n\u003Cul>\r\n\u003Cli>Why so many traditional SI tools (ODT, ZQ cal, etc.) are not present\u003C/li>\r\n\u003Cli>IDD Specification\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Power Management\r\n\u003Cul>\r\n\u003Cli>Power Down\u003C/li>\r\n\u003Cli>Clock Throttling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Initialization, Calibration, and Training\r\n\u003Cul>\r\n\u003Cli>JEDEC Initialization\r\n\u003Cul>\r\n\u003Cli>Mode Registers\u003C/li>\r\n\u003Cli>Initialization Steps\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Calibration and Training\r\n\u003Cul>\r\n\u003Cli>Vref Training\u003C/li>\r\n\u003Cli>Loopback LFSR MISR Training\r\n\u003Cul>\r\n\u003Cli>Command Bus (AWORD) Training\u003C/li>\r\n\u003Cli>Data Group (DWORD) Training\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Duty Cycle Adjustment (DCA) and Duty Cycle Monitoring (DCM)\u003C/li>\r\n\u003Cli>WDQS Interval Oscillator\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Errors and Error Handling\r\n\u003Cul>\r\n\u003Cli>Temperature\u003C/li>\r\n\u003Cli>Address Parity\u003C/li>\r\n\u003Cli>Data Parity\u003C/li>\r\n\u003Cli>Lane Remapping\u003C/li>\r\n\u003Cli>Sideband ECC\u003C/li>\r\n\u003Cli>On-Die ECC\u003C/li>\r\n\u003Cli>Post Package Repair\r\n\u003Cul>\r\n\u003Cli>Self-Repair\u003C/li>\r\n\u003Cli>Hard and Soft Repair\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Overview of IEEE 1500\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","hbm-elearning-course","\u003Cul>\r\n\u003Cli>DRAM architecture fundamentals\u003C/li>\r\n\u003Cli>Where JEDEC expects HBM to be placed in a system\u003C/li>\r\n\u003Cli>Organization and operation of HBM devices\u003C/li>\r\n\u003Cli>Electrical characteristics of HBM and why HBM lacks many SI tools found in other technologies\u003C/li>\r\n\u003Cli>Differences between WideIO, WideIO2, HBM1, HBM2, HBM2E, HBM3, HBM3E, HBM4 and HBM4E\u003C/li>\r\n\u003Cli>HBM3/HBM3E/HBM4/HBM4E bank state machine, commands and waveforms\u003C/li>\r\n\u003Cli>Overview of IEEE 1500\u003C/li>\r\n\u003Cli>Calibration and training of HBM channels\u003C/li>\r\n\u003Cli>HBM power management\u003C/li>\r\n\u003Cli>HBM error handling\u003C/li>\r\n\u003C/ul>","\u003Cp>Basic knowledge of digital design and computer architecture is recommended\u003C/p>","2026-02-02 18:15:54","02/01/26",{"id":253,"name":254,"about":255,"description":256,"slug":257,"instructor_fullname":161,"instructor_email":162,"equivelent_of":21,"subscription_length":48,"price":49,"price_arbor":188,"course_category_id":25,"you_will_learn":258,"prerequisites":51,"is_active":52,"modified_at":67,"presentation_id":259,"release_date":114},1713,"ARM Architecture eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARM Architecture\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>ARM processors are at the heart of many mobile phones, digital cameras, and other small portable devices. One characteristic of the processor that leads to this wide use is the low power consumption – a critical factor when battery life is a key product requirement. ARM processors are also heavily used in embedded control applications. As the mobile phone has evolved into an internet device with the tasks more typically associated with a PC (web browsing, media playback, etc), the processing capability has grown, such that the “simple” phone processor is now a much more capable device, a multiple core device that has the capability to move into the data center. This class looks at the range of processors comprising the ARMv7 architecture and the upcoming ARMv8 64-bit architecture, how the processors across the range are similar yet target different markets, and compare the architecture with Intel’s IA-32 architecture.\u003C/p>","comprehensive-arm-architecture-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>ARM architecture: ARMv7 (32-bit) and ARMv8 (64-bit) architectures, along with some of the history\u003C/li>\r\n\u003Cli>ARM microarchitecture, the internals of some of the different processors comprising the Cortex family\u003C/li>\r\n\u003Cli>Comparisons and contrasts with the Intel IA-32 architecture and microarchitectures\u003C/li>\r\n\u003Cli>Buses connecting the processor core(s) to the rest of the system\u003C/li>\r\n\u003Cli>Numerous examples of how this is used in SoC (System on a Chip) designs\u003C/li>\r\n\u003Cli>The ARM business and licensing model, and how this leads to a variety of devices\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>",375,{"id":261,"name":262,"about":263,"description":264,"slug":265,"instructor_fullname":161,"instructor_email":162,"equivelent_of":11,"subscription_length":48,"price":266,"price_arbor":266,"course_category_id":25,"you_will_learn":267,"prerequisites":240,"is_active":52,"modified_at":67,"presentation_id":268,"release_date":114},1714,"Fundamentals of ARMv8-A eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARMv8-A\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cdiv>This course is a subset of MindShare's course \u003Ca href=\"../../eLearning/Course/Comprehensive_ARM_Architecture_eLearning_Course\">\u003Cu>Comprehensive ARM Architecture\u003C/u>\u003C/a>. Modules 15-21 of that course have been extracted and offered here as a standalone course covering the basics of ARM's 64-bit architecture for the -A profile, often referred to as ARMv8.\u003C/div>","fundamentals-of-armv8-a-elearning-course","295","\u003Cul>\r\n\u003Cli>Basics of ARMv8-A\u003C/li>\r\n\u003C/ul>",377,{"id":270,"name":271,"about":272,"description":273,"slug":274,"instructor_fullname":45,"instructor_email":46,"equivelent_of":21,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":13,"you_will_learn":275,"prerequisites":276,"is_active":52,"modified_at":277,"presentation_id":278,"release_date":114},1751,"USB4 Architecture eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"USB4\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>If you are going to take one course on USB4, this should be it. MindShare's USB4 eLearning course is an exhaustive tutorial on USB4 from the electrical PHY all the way up to the Connection Manager (CM). It starts with a high-level view of the architecture, including the background of Thunderbolt to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.\u003C/p>","usb4-architecture-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>How a Type-C port determines it should operate as USB4\u003C/li>\r\n\u003Cli>Details of tunneling PCIe, DisplayPort and USB3 (ESS) across USB4 links\u003C/li>\r\n\u003Cli>How the Connection Manager discovers and enumerates USB4 Routers\u003C/li>\r\n\u003Cli>Interaction between the Host I/F Adapter and the Connection Manager using Tx and Rx Rings\u003C/li>\r\n\u003Cli>Routing of USB4 TLPs based on HopID and routing tables\u003C/li>\r\n\u003Cli>Flow control schemes employed in USB4\u003C/li>\r\n\u003Cli>Low-level initialization and training of a USB4 link\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>None is required, but some background in USB, PCIe, or Thunderbolt protocols would be helpful.\u003C/p>","2025-08-04 16:43:23",497,{"id":280,"name":281,"about":282,"description":283,"slug":284,"instructor_fullname":75,"instructor_email":76,"equivelent_of":13,"subscription_length":48,"price":285,"price_arbor":285,"course_category_id":23,"you_will_learn":286,"prerequisites":240,"is_active":52,"modified_at":67,"presentation_id":287,"release_date":55},1718,"SATA 3.2 Technology eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"SATA\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare brings the SATA course to life through its interactive classroom style, demonstrations, and hands-on exercises. This course covers the SATA 3.2 specification from a hardware design perspective and also discusses the software requirements of SATA implementations (Includes SATA Express and M.2). The Advanced Host Controller Interface (AHCI) is also described along with its numerous registers.\u003C/p>","sata-32-technology-elearning-course","795","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>The sequence of events associated with SATA initialization, including Out Of Band (OOB) signaling\u003C/li>\r\n\u003Cli>Details regarding the implementation and operation of the Advanced Host Controller Interface (AHCI)\u003C/li>\r\n\u003Cli>How to verify proper command protocol associated with each of the command categories\u003C/li>\r\n\u003Cli>How to verify proper control protocol associated with writes to the Control register\u003C/li>\r\n\u003Cli>The actions taken by each layer in the SATA interface\u003C/li>\r\n\u003Cli>The details associated with the implementation of Port Multipliers\u003C/li>\r\n\u003Cli>The operation and performance advantages of Native Command Queuing (NCQ)\u003C/li>\r\n\u003Cli>The new features associated with the SATA Express SSDs and M.2 mobile cards\u003C/li>\r\n\u003Cli>How the three SATA Express drives are detected\u003C/li>\r\n\u003Cli>The mating compatibility of the SATA Express plug and receptacles\u003C/li>\r\n\u003Cli>The compatibility associated with the M.2 modules and sockets\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>",385,{"id":289,"name":290,"about":291,"description":292,"slug":293,"instructor_fullname":75,"instructor_email":76,"equivelent_of":11,"subscription_length":48,"price":141,"price_arbor":141,"course_category_id":23,"you_will_learn":294,"prerequisites":295,"is_active":52,"modified_at":67,"presentation_id":296,"release_date":114},1764,"NVMe-oF eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"NVMe-oF\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare's NVMe-oF (Non-Volatile Memory Express – over Fabrics) course begins with a brief review of NVMe basics, discusses the forces driving the migration of NVMe into network fabrics, followed by an overview of the different fabrics NVMe-oF will work over such as Ethernet, InfiniBand and Fibre Channel. Finally, the details of NVMe over fabrics are described. \u003C/p>","nvme-of-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>An overview of the storage fabrics in use today, and their strengths and weaknesses\u003C/li>\r\n\u003Cli>The changes needed for NVMe to work in a fabric environment\u003C/li>\r\n\u003Cli>How an NVMe host discovers and accesses drives on the fabric\u003C/li>\r\n\u003Cli>How NVMe-oF provides a combination of attractive features for a storage fabric\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>NVMe architecture knowledge and previous exposure to PCIe is needed, as is some general knowledge of PC architectures.\u003C/p>",517,{"id":298,"name":299,"about":255,"description":300,"slug":301,"instructor_fullname":161,"instructor_email":162,"equivelent_of":11,"subscription_length":48,"price":302,"price_arbor":302,"course_category_id":25,"you_will_learn":303,"prerequisites":51,"is_active":52,"modified_at":67,"presentation_id":304,"release_date":114},1739,"Fundamentals of ARM Architecture eLearning Course","\u003Cp>This fundamentals course is a great start for any hardware or software engineer looking to get a base understanding of the ARM architecture. Topics range from the ARM instruction sets, processor modes, architecture profiles, instruction pipelines, bus interfaces, software development environments and much more.\u003C/p>","fundamentals-of-arm-architecture","195","\u003Cul>\r\n\u003Cli>Variety of ARM processors\u003C/li>\r\n\u003Cli>Terminology\u003C/li>\r\n\u003Cli>32-bit and 64-bit architectures\u003C/li>\r\n\u003Cli>System buses\u003C/li>\r\n\u003Cli>Software development environment\u003C/li>\r\n\u003C/ul>",471,{"id":306,"name":307,"about":308,"description":309,"slug":310,"instructor_fullname":45,"instructor_email":46,"equivelent_of":9,"subscription_length":48,"price":90,"price_arbor":67,"course_category_id":30,"you_will_learn":311,"prerequisites":51,"is_active":52,"modified_at":312,"presentation_id":313,"release_date":55},1752,"x86 Architecture eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"x86\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>\u003Cspan style=\"color: rgb(224, 62, 45);\">\u003Cstrong>Note: this course is a subset of our Intel Processor and Platform eLearning Course.\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>This course will be useful for anyone dealing with designing, verifying, validating, debugging, or developing for x86-based platforms. The x86 instruction set architecture has evolved over a period of almost 40 years. This course describes numerous aspects of the current architecture but also explains how we got to the current architecture based on the history and decisions made. It doesn't matter whether you're a hardware engineer or a software developer, this course has an enormous amount of relevant info for you.\u003C/p>","x86-architecture-elearning-course","\u003Cul>\r\n\u003Cli>x86 architecture basics like an overview of the instruction set, register set and operating modes\u003C/li>\r\n\u003Cli>The behavior of segmentation, how it was originally intended to be used and how it is actually used by operating systems today (both 32-bit and 64-bit OSs)\u003C/li>\r\n\u003Cli>How to setup system calls using multiple methods (and what are benefits / side-effects of each)\u003C/li>\r\n\u003Cli>How to setup interrupt service routines for both software and hardware interrupts as well as exceptions\u003C/li>\r\n\u003Cli>How to implement paging in both the 32-bit environments as well as the 64-bit environments including using various page sizes\u003C/li>\r\n\u003Cli>What the concepts of virtualization are and the behavior of the x86 hardware extensions for virtualization (including benefits and side-effects)\u003C/li>\r\n\u003C/ul>","2025-08-05 14:42:57",496,{"id":315,"name":316,"about":263,"description":317,"slug":318,"instructor_fullname":161,"instructor_email":162,"equivelent_of":21,"subscription_length":48,"price":150,"price_arbor":150,"course_category_id":25,"you_will_learn":319,"prerequisites":240,"is_active":52,"modified_at":67,"presentation_id":320,"release_date":55},1720,"ARM 64-bit Architecture (ARM v8-A) eLearning Course","\u003Cp>This course covers the 64-bit ARMv8-A architecture that follows on from and offers compatibility with the earlier ARMv7-A 32-bit architecture. Examples of processors that first implemented this 64-bit architecture are the ARM Cortex-A53 and Cortex A57 processors. Since the successful introduction of the ARMv8-A architecture and products, there have been several architectural enhancements. \u003C/p>","arm-64-bit-architecture-arm-v8-a-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>ARM architecture (ARMv8-A)\u003C/li>\r\n\u003Cli>Support for execution of 32-bit ARMv7-A code\u003C/li>\r\n\u003Cli>64-bit ISA (registers, instruction set, system instructions, etc)\u003C/li>\r\n\u003Cli>Floating point and Neon\u003C/li>\r\n\u003Cli>Calling conventions\u003C/li>\r\n\u003Cli>Memory and paging\u003C/li>\r\n\u003Cli>Exception and Interrupt handling, and the exception levels\u003C/li>\r\n\u003Cli>Virtualization (Exception Level 2)\u003C/li>\r\n\u003Cli>TrustZone overview (Exception Level 3)\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003Cli>Debug\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>",413,{"id":322,"name":323,"about":324,"description":325,"slug":326,"instructor_fullname":62,"instructor_email":63,"equivelent_of":11,"subscription_length":48,"price":266,"price_arbor":266,"course_category_id":13,"you_will_learn":327,"prerequisites":51,"is_active":52,"modified_at":67,"presentation_id":328,"release_date":114},1730,"USB Type-C and Power Delivery eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"USB Type-C\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>This introductory course is primarily concerned with topics described in two documents: USB Type-C Cable and Connector Specification and the USB Power Delivery Specification. The USB Type-C connectors address several limitations of traditional USB Type A and Type B connectors related to size, mechanical reliability, and the need to maintain proper cable and plug orientation. Type-C connector and cables have no required orientation and support USB 2.0, USB 3.1, as well as sideband signals for communications, audio, HDMI, or other purposes. In addition, Type-C brings a new set of power delivery capabilities as defined in USB Power Delivery Specification, including negotiated switching of upstream/downstream port roles and the device responsible for sourcing VBUS power.\u003C/p>","usb-type-c-and-power-delivery-elearning-course","\u003Cul>\r\n\u003Cli>Features of Type-C and Power Delivery\u003C/li>\r\n\u003Cli>Advantages of Type-C Cables\u003C/li>\r\n\u003Cli>Motivations for Power Delivery\u003C/li>\r\n\u003Cli>Advantages of Electrically Marked Cables\u003C/li>\r\n\u003Cli>Start Of Packet Messages\u003C/li>\r\n\u003Cli>Power Contract Negotiation\u003C/li>\r\n\u003C/ul>",439,{"id":330,"name":331,"about":332,"description":333,"slug":334,"instructor_fullname":161,"instructor_email":162,"equivelent_of":9,"subscription_length":48,"price":285,"price_arbor":285,"course_category_id":25,"you_will_learn":335,"prerequisites":240,"is_active":52,"modified_at":67,"presentation_id":336,"release_date":114},1731,"ARM Cortex-M7 Processor eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARM Cortex-M7\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>The ARM Cortex-M7 Architecture eLearning course focuses on software aspects of the ARMv7-M Architecture profiles (Cortex-M7). This course is aimed at embedded software and systems developers who wish to acquire a broad knowledge of ARM technology with a bias toward the microcontroller market.\u003C/p>","arm-cortex-m7-processor-elearning-course","\u003Cul>\r\n\u003Cli>Architectural Features of the M7 Processor\u003C/li>\r\n\u003Cli>Powerful & Scalable Instruction Set\u003C/li>\r\n\u003Cli>Interrupts and Exceptions\u003C/li>\r\n\u003Cli>System Interface Architecture\u003C/li>\r\n\u003Cli>Caches\u003C/li>\r\n\u003Cli>Memory Model\u003C/li>\r\n\u003Cli>Assembler Programming intro\u003C/li>\r\n\u003Cli>Debug Features / Techniques\u003C/li>\r\n\u003C/ul>",442,{"id":338,"name":339,"about":340,"description":341,"slug":342,"instructor_fullname":62,"instructor_email":230,"equivelent_of":25,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":30,"you_will_learn":343,"prerequisites":78,"is_active":52,"modified_at":344,"presentation_id":345,"release_date":55},1735,"Intel x86 Processor and Platform Architecture eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"Intel Processors and Platforms\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>Each CPU and chipset generation brings new capabilities while maintaining backward compatibility with earlier platforms. New 9th and 10th generation CPU architectures offer significant improvements in instruction throughput, power conservation, integrated graphics, security, system-on-a-chip (SOC) packaging options, etc. This 5-day course introduces the x86 Instruction Set Architecture (ISA) and describes the hardware features of the latest Intel Core and Xeon CPUs supporting it. In addition, the course presents an overview of memory, platform controller hub (PCH) logic, and IO interfaces that may be employed when implementing common system types.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>A full understanding of an Intel x86 hardware platform includes knowledge of CPU/PCH capabilities, BIOS/OS setup of programmable platform features, as well as the dynamic status of the system with regards to thermal and error events, etc. MindShare Arbor demonstrations integrated into this course present a decoded view of register setup, system and device status, as well as a coherent summary of platform information reported when the CPUID instruction is executed. Students may use Arbor software for real-time scans of local systems, read/modify specific registers, and even save Arbor scan results for later sharing and off-line review.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>This course is updated as frequently as possible in an attempt to provide a “snapshot” of Intel Core and Xeon x86 platform components and system implementations. Content is based on publicly available documents.\u003C/p>","intel-x86-processor-and-platform-architecture-elearning-course","\u003Cul>\r\n\u003Cli>Intel x86 CPU and Chipset Evolution\u003C/li>\r\n\u003Cli>Current Core and Xeon CPUs: Ice Lake, Cascade Lake, plus “Refresh” Variants\u003C/li>\r\n\u003Cli>x86 Instruction Set Architecture (ISA) and CPU Operating Modes\u003C/li>\r\n\u003Cli>Core and Xeon CPU Microarchitecture Differences\u003C/li>\r\n\u003Cli>Caches\u003C/li>\r\n\u003Cli>Platform Addressing\u003C/li>\r\n\u003Cli>Main Memory DRAM\u003C/li>\r\n\u003Cli>Ultra Path Interconnect (UPI)\u003C/li>\r\n\u003Cli>CPU Integrated Graphics\u003C/li>\r\n\u003Cli>CPU Integrated IO (IIO)\u003C/li>\r\n\u003Cli>Interrupt Handling\u003C/li>\r\n\u003Cli>Hardware Virtualization Support\u003C/li>\r\n\u003Cli>Platform Controller Hub (PCH) Features\u003C/li>\r\n\u003Cli>Power and Thermal Management\u003C/li>\r\n\u003Cli>CPU Performance Monitoring\u003C/li>\r\n\u003C/ul>","2025-08-05 14:37:08",458,{"id":347,"name":348,"about":349,"description":350,"slug":351,"instructor_fullname":75,"instructor_email":76,"equivelent_of":21,"subscription_length":48,"price":100,"price_arbor":188,"course_category_id":23,"you_will_learn":352,"prerequisites":51,"is_active":52,"modified_at":353,"presentation_id":67,"release_date":251},1816,"NVMe 2.x eLearning Course","\u003Cp>MindShare's NVMe (Non-Volatile Memory Express) 2.x course begins with a high-level view of this storage architecture to give the big-picture context for hardware and software interactions. We drill down into details for each aspect of NVMe. Next, we review all the changes and added features to the more recent spec revisions. Since NVMe-oF (NVMe over Fabrics) was combined with the original NVMe definition in the 2.0 spec revision, we include a thorough coverage of that as well. Finally, because many implementations of NVMe will use PCI Express (PCIe), a brief overview of that interface is included.\u003C/p>","\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>Covered in the NVMe 1.4 eLearning course (included)\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>PCIe Architecture Overview\r\n\u003Cul>\r\n\u003Cli>Introduction\u003C/li>\r\n\u003Cli>Basic operation\u003C/li>\r\n\u003Cli>Transaction types\u003C/li>\r\n\u003Cli>Layers and responsibilities overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>NVMe Introduction\r\n\u003Cul>\r\n\u003Cli>NVMe concepts and definitions\u003C/li>\r\n\u003Cli>Comparison with SATA\u003C/li>\r\n\u003Cli>NVMe Host-Controller Interface overview\u003C/li>\r\n\u003Cli>Queue Management\r\n\u003Cul>\r\n\u003Cli>Doorbell Head and Tail registers\u003C/li>\r\n\u003Cli>Execution sequence\u003C/li>\r\n\u003Cli>Tracking completion status\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Commands\r\n\u003Cul>\r\n\u003Cli>NVMe Admin Commands\u003C/li>\r\n\u003Cli>General Structure of commands\u003C/li>\r\n\u003Cli>Identify command options and results\u003C/li>\r\n\u003Cli>Creation and management of Queues\u003C/li>\r\n\u003Cli>Asynchronous Event Notification\u003C/li>\r\n\u003Cli>NVMe IO Commands\r\n\u003Cul>\r\n\u003Cli>Read and Write command structure\u003C/li>\r\n\u003Cli>Optimizing write commands\u003C/li>\r\n\u003Cli>Avoiding write amplification\u003C/li>\r\n\u003Cli>Buffer addressing modes (PRPs vs. SGLs)\u003C/li>\r\n\u003Cli>Priority and Arbitration of commands\u003C/li>\r\n\u003Cli>Completing commands\u003C/li>\r\n\u003Cli>Handling Metadata (DIF/DIX)\u003C/li>\r\n\u003Cli>Get Features / Set Features – full coverage of features\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cul>\r\n\u003Cli>Architecture\r\n\u003Cul>\r\n\u003Cli>Error reporting, Error Reporting Structures\r\n\u003Cul>\r\n\u003Cli>Asynchronous Events\u003C/li>\r\n\u003Cli>Completion status\u003C/li>\r\n\u003Cli>Log pages\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Other log pages\u003C/li>\r\n\u003Cli>Firmware updates\u003C/li>\r\n\u003Cli>Controller registers\u003C/li>\r\n\u003Cli>Controller initialization\u003C/li>\r\n\u003Cli>Power Management\u003C/li>\r\n\u003Cli>Reservations\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\"> Other NVMe commands\r\n\u003Cul>\r\n\u003Cli>Write uncorrectable\u003C/li>\r\n\u003Cli>Write zeroes\u003C/li>\r\n\u003Cli>Compare\u003C/li>\r\n\u003Cli>Dataset management\u003C/li>\r\n\u003Cli>Configuration overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Summary of changes for 1.3\r\n\u003Cul>\r\n\u003Cli>Boot partitions\u003C/li>\r\n\u003Cli>Thermal management by host\u003C/li>\r\n\u003Cli>Write streams\u003C/li>\r\n\u003Cli>Deallocation\u003C/li>\r\n\u003Cli>Virtualization support\u003C/li>\r\n\u003Cli>Debug support – Telemetry, initiated by host or device\u003C/li>\r\n\u003Cli>Self-test options\u003C/li>\r\n\u003Cli>Sanitize command\u003C/li>\r\n\u003Cli>New commands\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Summary of changes for 1.4\r\n\u003Cul>\r\n\u003Cli>NVM Sets\u003C/li>\r\n\u003Cli>I/O Determinism\u003C/li>\r\n\u003Cli>Read recovery levels\u003C/li>\r\n\u003Cli>Persistent Memory Region (PMR)\u003C/li>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Asymmetric Namespace Access (ANA)\u003C/span>\u003C/li>\r\n\u003Cli>Namespace write protect\u003C/li>\r\n\u003Cli>Persistent event log\u003C/li>\r\n\u003Cli>Rebuild assist\u003C/li>\r\n\u003Cli>Endurance groups\u003C/li>\r\n\u003Cli>I/O Performance and Endurance Hints\u003C/li>\r\n\u003Cli>Traffic-based Keep Alive\u003C/li>\r\n\u003Cli>Vendor-specific UUIDs\u003C/li>\r\n\u003Cli>Verify - new command\u003C/li>\r\n\u003Cli>Administrative controller\u003C/li>\r\n\u003Cli>SQ Associations\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cstrong>\u003Cspan style=\"color: rgb(186, 55, 42);\">Covered in the NVMe 2.x eLearning course (included)\u003C/span>\u003C/strong>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>Summary of select updates from 2.0 through 2.3 specs\r\n\u003Cul>\r\n\u003Cli>Simple copy command \u003C/li>\r\n\u003Cli>Domains and Partitioning\u003C/li>\r\n\u003Cli>NVM Set and Endurance Group Management\u003C/li>\r\n\u003Cli>Command and Feature Lockdown\u003C/li>\r\n\u003Cli>NVMe KV\u003C/li>\r\n\u003Cli>Zoned Namespaces\u003C/li>\r\n\u003Cli> Namespace types\u003C/li>\r\n\u003Cli>IO Command Set Independent Data Structure\u003C/li>\r\n\u003Cli>Rotational media support\u003C/li>\r\n\u003Cli>Command and Effect Log (CEL) Enhancements\u003C/li>\r\n\u003Cli>Non-MDT Command Size Limits\u003C/li>\r\n\u003Cli>CMB Write Elasticity Status\u003C/li>\r\n\u003Cli>Multiple Controller Firmware Update\u003C/li>\r\n\u003Cli> Telemetry Log Size Changes\u003C/li>\r\n\u003Cli>Telemetry Enhancements\u003C/li>\r\n\u003Cli>Namespace Attachment Limits\u003C/li>\r\n\u003Cli>Time To Ready Enhancements\u003C/li>\r\n\u003Cli>Graceful Disconnection\u003C/li>\r\n\u003Cli>Persistent Event Log Context Counter\u003C/li>\r\n\u003Cli> SGL Optimizations\u003C/li>\r\n\u003Cli>Protection Information Enhancement\u003C/li>\r\n\u003Cli>ZNS Status Code and Async Notification\u003C/li>\r\n\u003Cli> Aborting Commands During Format NVM Command\u003C/li>\r\n\u003Cli>Multiple Controller Shutdown Enhancement\u003C/li>\r\n\u003Cli> Persistent Event Log (PEL) State and Source Reporting\u003C/li>\r\n\u003Cli>Get Log Page Index Offsets\u003C/li>\r\n\u003Cli>In-band Authentication Protocol for NVMe over Fabrics\u003C/li>\r\n\u003Cli>Transport Layer Security (TLS) 1.3 Support\u003C/li>\r\n\u003Cli>Set/Get Features Ported from NVMe-MI to the NVMe 2.0 Base Spec\u003C/li>\r\n\u003Cli> Boot Partition Read Access using OOB\u003C/li>\r\n\u003Cli>Additional Controller Metadata Types\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cstrong>\u003Cspan style=\"color: rgb(186, 55, 42);\">Covered in the NVMe-oF eLearning course (included)\u003C/span>\u003C/strong>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>Introduction\r\n\u003Cul>\r\n\u003Cli>Motivation for moving NVMe to fabrics\r\n\u003Cul>\r\n\u003Cli>Improve storage network performance\u003C/li>\r\n\u003Cli>Avoid limitations of PCIe, extend NVMe protocol to the fabric\u003C/li>\r\n\u003Cli>Optimize access latency across the network\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Differences from base NVMe\u003C/li>\r\n\u003Cli>Initialization Background\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Fabric Discovery\r\n\u003Cul>\r\n\u003Cli>Discovery Service, Discovery Controllers\u003C/li>\r\n\u003Cli>Discovery Mechanism\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>NVMe-oF Initialization\r\n\u003Cul>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Fabrics Commands\u003C/span>\u003C/li>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Device Setup\u003C/span>\u003C/li>\r\n\u003Cli>Transport mapping/binding RDMA\u003C/li>\r\n\u003Cli>Introduction to RDMA (Remote Direct Memory Access)\u003C/li>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Protocol Translation\u003C/span>\u003C/li>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">RDMA Examples\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>RDMA Concepts\r\n\u003Cul>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Motivation: Kernel bypass – reduce CPU involvement\u003C/span>\u003C/li>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Zero-copy operation when possible\u003C/span>\u003C/li>\r\n\u003Cli>RNIC (RDMA-aware Network Interface Card)\u003C/li>\r\n\u003Cli>Pinned remote memory and storage\u003C/li>\r\n\u003Cli>Command-based Flow Control\u003C/li>\r\n\u003Cli>Read and Write Command Examples\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>NVMe-oF Details\r\n\u003Cul>\r\n\u003Cli>Controller Initialization\u003C/li>\r\n\u003Cli>Connections and Associations\u003C/li>\r\n\u003Cli>Static vs. Dynamic Controller model\u003C/li>\r\n\u003Cli>Properties instead of registers\u003C/li>\r\n\u003Cli>Authentication\u003C/li>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Encapsulation\u003C/span>\u003C/li>\r\n\u003Cli>\u003Cspan lang=\"PT-BR\">Accessing RDMA Queue pairs\u003C/span>\u003C/li>\r\n\u003Cli>Data transfer: Command, Response, Data, Flow Control\u003C/li>\r\n\u003Cli>Fabrics Commands and Responses\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>RNIC Details\r\n\u003Cul>\r\n\u003Cli>Software Layers\u003C/li>\r\n\u003Cli>RDMA Verbs\u003C/li>\r\n\u003Cli>Memory Regions and Windows\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Ethernet overview\r\n\u003Cul>\r\n\u003Cli>TCP/IP: addressing, layers, packets\u003C/li>\r\n\u003Cli>RDMA models added to it: RoCE and iWARP\r\n\u003Cul>\r\n\u003Cli>Overview of iWARP\r\n\u003Cul>\r\n\u003Cli>Added to TCP/IP, so packets are routable and don’t need DCB\u003C/li>\r\n\u003Cli>Messages\u003C/li>\r\n\u003Cli>Layers\u003C/li>\r\n\u003Cli>Advantages and disadvantages\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Overview of RoCE\r\n\u003Cul>\r\n\u003Cli>Version 2 packets include routing information, version 1 did not\u003C/li>\r\n\u003Cli>Use of Data Center Bridging (DCB) to manage routing\u003C/li>\r\n\u003Cli>Flow control\u003C/li>\r\n\u003Cli>Soft RoCE\u003C/li>\r\n\u003Cli>Advantages and disadvantages\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","nvme-2x-elearning-course","\u003Cul>\r\n\u003Cli>Basics of the NVMe Host Controller Interface model\u003C/li>\r\n\u003Cli>The steps for device initialization\u003C/li>\r\n\u003Cli>How command queues are set up and managed\u003C/li>\r\n\u003Cli>How the host software\r\n\u003Cul>\r\n\u003Cli>Informs the controller of new commands to execute\u003C/li>\r\n\u003Cli>Learns that commands have been completed\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>The list of defined commands and how they work\u003C/li>\r\n\u003Cli>How error reporting structures are defined\u003C/li>\r\n\u003Cli>Power management options\u003C/li>\r\n\u003Cli>The new features added with the more recent revisions to the spec (thru 2.2)\u003C/li>\r\n\u003Cli>An overview of the storage fabrics in use today, and their strengths and weaknesses\u003C/li>\r\n\u003Cli>The changes needed for NVMe to work in a fabric environment\u003C/li>\r\n\u003Cli>How an NVMe host finds and accesses drives on a fabric\u003C/li>\r\n\u003Cli>How NVMe-oF provides a combination of attractive features for a storage fabric\u003C/li>\r\n\u003C/ul>","2026-02-02 20:47:06",{"id":355,"name":356,"about":357,"description":358,"slug":359,"instructor_fullname":62,"instructor_email":230,"equivelent_of":13,"subscription_length":48,"price":90,"price_arbor":90,"course_category_id":16,"you_will_learn":360,"prerequisites":51,"is_active":52,"modified_at":361,"presentation_id":362,"release_date":55},1759,"I3C Architecture eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"I3C\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>This MindShare course is designed for hardware/software engineers and others needing detailed coverage of MIPI I3C protocol. \u003C/p>","i3c-architecture-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Major features defined in the MIPI I3C Basic Specification\u003C/li>\r\n\u003Cli>How MIPI I3C addresses some of the long-standing speed, power, and pin count limitations of alternative IC communication protocols, including I2C and SPI\u003C/li>\r\n\u003Cli>Why I3C devices dynamically switch data drivers between push-pull and open drain signaling\u003C/li>\r\n\u003Cli>The motivations for MIPI I3C Hot-Join in power sensitive applications\u003C/li>\r\n\u003Cli>How I3C compliant devices report bus and internal characteristics to software\u003C/li>\r\n\u003Cli>How an enhanced set of direct and broadcast Common Command Code (CCC) transactions help simplify initialization, changing bus modes, and with device control and status operations\u003C/li>\r\n\u003Cli>The use of I3C in-band interrupts (IBI) to reduce pin count and enable devices to send critical status information as part of the IBI payload.\u003C/li>\r\n\u003Cli>Key features of the MIPI I3C Host Controller Interface (HCI) Specification\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","2025-01-02 17:08:27",506,{"id":364,"name":365,"about":366,"description":367,"slug":368,"instructor_fullname":161,"instructor_email":162,"equivelent_of":13,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":5,"you_will_learn":369,"prerequisites":370,"is_active":52,"modified_at":371,"presentation_id":372,"release_date":55},1762,"PCIe Security eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PCIe Security\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cdiv>This PCIe focused security course starts by looking at some of the simpler forms of attacks such as DMA, and some of the defenses again those attacks (IOMMU), and also some of the holes in these defense mechanisms. We then move onto looking at some of the additional features added to help protect the fabric (such as source validation in Access Control Services), and then onto the newest features for evaluating trust, link encryption, and point-to-point encryption. We also look at the supported for a TEE (Trusted Execution Environment) VM.\u003C/div>","pcie-security-elearning-course","\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Threat models.\u003C/li>\r\n\u003Cli>STRIDE categories (spoofing, tampering, repudiation, information disclosure, repudiation, denial of service, elevation of privilege).\u003C/li>\r\n\u003Cli>System and PCIe overview, highlighting the areas we will discuss with respect to attacks.\u003C/li>\r\n\u003Cli>DMA attacks.\u003C/li>\r\n\u003Cli>Using the IOMMU to prevent DMA attacks, and the potential security holes with an IOMMU.\u003C/li>\r\n\u003Cli>Other DMA attack mitigations such as encrypted memory.\u003C/li>\r\n\u003Cli>Interrupt attacks.\u003C/li>\r\n\u003Cli>Using Interrupt Remapping to prevent interrupt attacks, and the security holes with interrupt remapping.\u003C/li>\r\n\u003Cli>The idea of mutable versus immutable, and why everything needs to be treated as mutable.\u003C/li>\r\n\u003Cli>Error reporting attacks.\u003C/li>\r\n\u003Cli>Switch attacks.\u003C/li>\r\n\u003Cli>The enhancements to the PCIe fabric and to manageability (CMA/SPDM/IDE)\u003C/li>\r\n\u003Cli>The boundaries of the protection from the enhancements, and possible paths to attacking such a secured system.\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>PCIe knowledge is recommended but not required.\u003C/p>","2026-04-21 13:48:55",514,{"id":374,"name":375,"about":376,"description":377,"slug":378,"instructor_fullname":88,"instructor_email":89,"equivelent_of":9,"subscription_length":48,"price":90,"price_arbor":188,"course_category_id":9,"you_will_learn":379,"prerequisites":380,"is_active":52,"modified_at":381,"presentation_id":67,"release_date":382},1818,"UCIe Fundamentals eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"UCIe\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare’s UCIe Fundamentals course provides a solid foundation to understanding die-to-die architecture and use of UCIe retimers to extend connectivity beyond the package. The course describes port architecture details including protocol layer, die-to-die adapter layer, logical physical layer and electrical physical layer. We describe single and multi-module configurations. In addition, the course describes the sideband architecture details. Sideband interface is used for back-channel Link training, access to registers, Link management packets and parameter exchanges with remote Link partner. UCIe register architecture and the mechanism by which UCIe-aware SW discovers UCIe capability is described. An optional section describes a Raw Die-to-Die Interface (RDI) and Flit-aware Die-to-Die Interface (FDI) between the die-to-die adapter layer and physical layer.\u003C/p>","ucie-fundamentals-elearning-course","\u003Cul>\r\n\u003Cli>UCIe system architecture used for die-to-die communication including use of UCIe retimers\u003C/li>\r\n\u003Cli>UCIe for tunneling PCIe, CXL and other protocols in raw mode\u003C/li>\r\n\u003Cli>UCIe port design constituting Protocol, Die-to-Die Adapter, Logical and Electrical Physical Layers\u003C/li>\r\n\u003Cli>Sideband interface usage and protocol\u003C/li>\r\n\u003Cli>Software view of UCIe when paired with PCIe or CXL protocol layers\u003C/li>\r\n\u003Cli>UCIe Interface (RDI and FDI) architecture between the Die-to-Die Adapter layer and Physical layer.\u003C/li>\r\n\u003C/ul>","\u003Cp>A good working knowledge of PCI Express (PCIe) and Compute Express Link (CXL) is a must. Computer architecture fundamentals. Some knowledge of Intel, AMD or Arm processor architectures.\u003C/p>","2026-06-04 15:50:43","05/23/26",{"id":384,"name":385,"about":386,"description":387,"slug":388,"instructor_fullname":75,"instructor_email":76,"equivelent_of":9,"subscription_length":48,"price":111,"price_arbor":90,"course_category_id":23,"you_will_learn":389,"prerequisites":51,"is_active":52,"modified_at":390,"presentation_id":391,"release_date":114},1746,"NVM Express 1.4 eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"NVMe\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>MindShare's NVMe (Non-Volatile Memory Express) 1.4 course begins with an optional review of PCI Express (PCIe) basics as a foundation for the study of NVMe. Next, a high-level view of the architecture provides the big-picture context of the hardware architecture and software interactions. Finally, we drill down into details for each aspect of the NVMe architecture. The course add details included in the 1.1, 1.2, 1.3 and 1.4 specs. \u003C/p>","nvm-express-14-elearning-course","\u003Cul>\r\n\u003Cli>Basics of the NVMe Host Controller Interface model\u003C/li>\r\n\u003Cli>The steps for device initialization\u003C/li>\r\n\u003Cli>How command queues are set up and managed\u003C/li>\r\n\u003Cli>How host software:\r\n\u003Cul>\r\n\u003Cli style=\"list-style-type: none;\">\r\n\u003Cul>\r\n\u003Cli>Informs the controller of new commands to execute\u003C/li>\r\n\u003Cli>Learns that commands have been completed\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>What commands are defined up to 1.4 spec, and how they work\u003C/li>\r\n\u003Cli>Error reporting structures\u003C/li>\r\n\u003Cli>Power management options\u003C/li>\r\n\u003Cli>Optional PCIe architecture overview on request\u003C/li>\r\n\u003C/ul>","2025-01-02 16:45:25",488,{"id":393,"name":394,"about":395,"description":396,"slug":397,"instructor_fullname":45,"instructor_email":46,"equivelent_of":21,"subscription_length":48,"price":100,"price_arbor":188,"course_category_id":19,"you_will_learn":398,"prerequisites":51,"is_active":52,"modified_at":399,"presentation_id":67,"release_date":400},1815,"IO Virtualization for ARM Platforms eLearning Course","\u003Cp>Virtualization is one of the hot, exciting areas in the industry today, generating significant revenue, and solving critical problems in data centers and in embedded and mobile markets. However, software virtualization techniques add too much overhead to allow virtualization to be used for some applications. This class will look at those problem applications and the hardware solutions architected by ARM as well as support in standards like PCI Express (PCIe). The course focuses on ARM SoCs that have hardware support for DMA remapping (System MMU - SMMU) and virtual interrupts (GICv3 and GICv4). The course also discusses details of Address Translation Services (ATS), Access Control Services (ACS) and Single-Root IOV (SRIOV) implementations (though not multi-root IOV MRIOV).\u003C/p>","\u003Cul>\r\n\u003Cli>Introduction to Virtualization\u003Cbr>\r\n\u003Cul>\r\n\u003Cli>What is virtualization\u003C/li>\r\n\u003Cli>Why is it important\u003C/li>\r\n\u003Cli>Software Techniques\u003C/li>\r\n\u003Cli>Performance Issues\u003C/li>\r\n\u003Cli>PCI Pass-through (DirectPath I/O)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>PCIe Address Translation Services (ATS)\r\n\u003Cul>\r\n\u003Cli>What it is and how it helps\r\n\u003Cul>\r\n\u003Cli>Performance benefits\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>ATS Protocol\r\n\u003Cul>\r\n\u003Cli>Changes to PCIe packets\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Address Translation Caches (ATCs)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>PCIe Access Control Services (ACS)\r\n\u003Cul>\r\n\u003Cli>What it is and why it's needed\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>PCIe Single-Root IO Virtualization (SRIOV)\r\n\u003Cul>\r\n\u003Cli>What it is and how it helps\u003C/li>\r\n\u003Cli>Functions vs. Physical Functions (PFs) vs. Virtual Functions (VFs)\u003C/li>\r\n\u003Cli>SRIOV Capability Structure (including VF BARs)\u003C/li>\r\n\u003Cli>Config space of VFs\u003C/li>\r\n\u003Cli>PCIe Alternative Routing ID (ARI)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>ARM SMMU: DMA Remapping\u003Cbr>\r\n\u003Cul>\r\n\u003Cli>What it is and how it helps\u003Cbr>\r\n\u003Cul>\r\n\u003Cli>Performance benefits\u003C/li>\r\n\u003Cli>Security benefits\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Virtual Address (VA) vs. Intermediate Physical Address (IPA) vs. Physical Addresses (PA)\u003C/li>\r\n\u003Cli>SMMU functionality and data structures\u003C/li>\r\n\u003Cli>Latency issues\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Shared Virtual Memory\r\n\u003Cul>\r\n\u003Cli>What it is and how it helps\u003C/li>\r\n\u003Cli>PCIe Process Space IDs (PASIDs)\u003C/li>\r\n\u003Cli>ARM SMMU support of PASIDs\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>ARM GICv3 / v4: Interrupt Remapping\r\n\u003Cul>\r\n\u003Cli>What it is and why it's needed\r\n\u003Cul>\r\n\u003Cli>Big security issue\u003C/li>\r\n\u003Cli>Virtualization performance improvements\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>MSI / MSI-X review (interrupt delivery)\u003C/li>\r\n\u003Cli>Shared Peripheral Interrupts (SPIs) vs Locality-specific Peripheral Interrupts (LPIs)\u003C/li>\r\n\u003Cli>Interrupt Translation Service (ITS)\r\n\u003Cul>\r\n\u003Cli>Virtual interrupts\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","io-virtualization-for-arm-platforms-elearning-course","\u003Cul>\r\n\u003Cli>What virtualization is, and the revenue generating uses for virtualization\u003C/li>\r\n\u003Cli>The major sources of overhead with software-only virtualization techniques\u003C/li>\r\n\u003Cli>How I/O virtualization will use the new hardware assists, to solve these problems\u003C/li>\r\n\u003Cli>ARM SMMU and ARM GICv3/v4\u003C/li>\r\n\u003Cli>DMA remapping (Intermediate Physical to Host Physical as well as Shared Virtual Memory)\u003C/li>\r\n\u003Cli>PCIe Address Translation Services (ATS)\u003C/li>\r\n\u003Cli>PCIe Access Control Services (ACS)\u003C/li>\r\n\u003Cli>Single-Root IOV (SRIOV)\u003C/li>\r\n\u003Cli>Process Address Space IDs (PASIDs)\u003C/li>\r\n\u003C/ul>","2026-06-15 14:16:44","04/01/26",{"id":402,"name":403,"about":404,"description":405,"slug":406,"instructor_fullname":161,"instructor_email":162,"equivelent_of":21,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":19,"you_will_learn":407,"prerequisites":78,"is_active":52,"modified_at":67,"presentation_id":408,"release_date":114},1738,"PC Virtualization eLearning Course","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PC Virtualization\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>Virtualization is one of the fascinating and complex areas in the PC industry, generating significant revenue, and solving critical problems in the PC data center. Virtualization technology is used across a wide range of platforms, from embedded to data center. This class is to explain what virtualization is, and what IT problems it solves, and also the problems that it does not solve. You will learn how Intel virtualization is implemented, along with the overhead and performance issues with the implementations.\u003C/p>","pc-virtualization-elearning-course","\u003Cul>\r\n\u003Cli>What virtualization is, and the revenue generating uses for virtualization.\u003C/li>\r\n\u003Cli>The theory of virtualization, dating back to the IBM mainframes of the 60s and 70s, and how that mainframe technology is relevant to PC virtualization today.\u003C/li>\r\n\u003Cli>How Intel has enhanced their processors to help implement classical virtualization.\u003C/li>\r\n\u003Cli>How memory and I/O virtualization is achieved today.\u003C/li>\r\n\u003Cli>The major sources of overhead with the virtualization techniques.\u003C/li>\r\n\u003C/ul>",468,{"id":410,"name":411,"about":412,"description":413,"slug":414,"instructor_fullname":62,"instructor_email":63,"equivelent_of":11,"subscription_length":48,"price":266,"price_arbor":266,"course_category_id":30,"you_will_learn":415,"prerequisites":51,"is_active":52,"modified_at":67,"presentation_id":416,"release_date":114},1740,"Thunderbolt 3 Fundamentals eLearning Course","\u003Cp>Let MindShare Bring \"Thunderbolt\" to Life for You\u003C/p>","\u003Cp>This course is designed with hardware, software and validation engineers in mind. System board and computer designers will benefit too. Major features of Thunderbolt (Type-C) connections and power delivery are described.\u003C/p>","thunderbolt-3-fundamentals-elearning-course","\u003Cul>\r\n\u003Cli>Thunderbolt features\u003C/li>\r\n\u003Cli>Thunderbolt applications\u003C/li>\r\n\u003Cli>Intel Thunderbolt Controller (Alpine Ridge) architecture\u003C/li>\r\n\u003Cli>Thunderbolt port (USB Type-C) architecture\u003C/li>\r\n\u003Cli>Thunderbolt port initialization\u003C/li>\r\n\u003Cli>Power Delivery messaging\u003C/li>\r\n\u003Cli>Thunderbolt 3 Electronically Marked Cable Assembly (EMCA)\u003C/li>\r\n\u003C/ul>",474,{"id":418,"name":419,"about":420,"description":421,"slug":422,"instructor_fullname":75,"instructor_email":76,"equivelent_of":28,"subscription_length":48,"price":100,"price_arbor":100,"course_category_id":5,"you_will_learn":423,"prerequisites":51,"is_active":52,"modified_at":424,"presentation_id":154,"release_date":425},1749,"PCIe 5.0 eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PCIe 5.0\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail. The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers.\u003C/p>","pcie5-elearning-course","\u003Cul>\r\n\u003Cli>PCI Express features and capabilities\u003C/li>\r\n\u003Cli>The definition and responsibilities of each of the layers in the interface\u003C/li>\r\n\u003Cli>How hardware-based automatic error detection and correction mechanism works\u003C/li>\r\n\u003Cli>The various additional levels of error detection and reporting\u003C/li>\r\n\u003Cli>The details of the packet-based protocol used by PCIe\u003C/li>\r\n\u003Cli>The address space and packet-routing methods used\u003C/li>\r\n\u003Cli>How the various power management techniques work\u003C/li>\r\n\u003Cli>Configuration register details that provide control and status visibility to software\u003C/li>\r\n\u003Cli>The purpose of equalization and how it is done in PCIe 3.0 and later\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>If you are going to take one course on PCI Express, this should be it. MindShare's PCIe eLearning course is an exhaustive tutorial on PCIe from the electrical PHY all the way up to software. It starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols.\u003C/p>","2026-10-22 16:35:30","11/13/24",{"id":427,"name":428,"about":429,"description":430,"slug":431,"instructor_fullname":161,"instructor_email":162,"equivelent_of":13,"subscription_length":48,"price":111,"price_arbor":111,"course_category_id":25,"you_will_learn":432,"prerequisites":240,"is_active":52,"modified_at":67,"presentation_id":433,"release_date":114},1711,"ARM 32-bit Architecture (ARM v7) eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARMv7\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>This was the only eLearning course endorsed by ARM for anyone wanting to take the ARM Accredited Engineer (AAE) certification exam when ARM was still offering their AAE certification program. That program has been discontinued by ARM, but the information in this course is still very relevant and extremely valuable for anyone working with ARM v7 architectures.\u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(108, 108, 108); font-size: 18px; font-weight: bold;\"> \u003C/span>\u003C/p>\r\n\u003Cp>\u003Cspan class=\"sectionsubhead\">ARM Endorsement\u003C/span>\u003C/p>\r\n\u003Cp style=\"padding-left: 40px;\">\u003Cem>“On the strength of MindShare’s position as an industry leader in technology training, particularly in the area of microprocessor architecture, we were happy to welcome them to the AAE program as an ARM Accreditation Training Partner (AATP). Their expertise in delivering engaging self-paced eLearning courses should make MindShare's ARM Accredited Engineer Certification eLearning course a very good way to efficiently and cost-effectively prepare for the ARM Accredited Engineer (AAE) exam”.\u003C/em>\u003Cbr>\u003Cstrong>- Daniel Dearing, AAE Program Manager\u003C/strong>\u003C/p>","arm-32-bit-architecture-arm-v7-elearning-course","\u003Cp>The ARM 32-bit Architecture eLearning course focuses on software-related aspects of the ARMv7 Architecture, with a specific focus on Cortex-A and Cortex-R profiles, plus common subjects like software tools. This course is aimed at embedded software and systems developers who would like to acquire a broad knowledge of ARM technology with a bias toward application processors and real-time processors.\u003C/p>",371,{"id":435,"name":436,"about":437,"description":438,"slug":439,"instructor_fullname":62,"instructor_email":63,"equivelent_of":11,"subscription_length":48,"price":64,"price_arbor":64,"course_category_id":13,"you_will_learn":440,"prerequisites":441,"is_active":52,"modified_at":67,"presentation_id":442,"release_date":114},1742,"USB 3.2 Update eLearning Course","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"USB 3.2\" to Life for You\u003C/strong>\u003C/span>\u003C/div>","\u003Cp>One of the most significant USB 3.2 enhancements is the option for dual-lane traffic on the Enhanced SuperSpeed (ESS) interface. Prior to USB 3.2, all generations of USB were based on single-lane serial bus communications. SuperSpeed and SuperSpeedPlus as defined in the USB 3.1 specification is a dual-simplex connection with one differential signal pair for each direction (Tx/Rx). With USB 3.2 dual-lane signaling uses two differential pairs in each direction.\u003C/p>","usb-32-update","\u003Cul>\r\n\u003Cli>USB 3.2 Topology Overview\u003C/li>\r\n\u003Cli>USB 3.2 Hub Requirements\u003C/li>\r\n\u003Cli>USB 3.2 Protocol and Link Layer Changes\u003C/li>\r\n\u003Cli>USB 3.2 Physical Layer\u003C/li>\r\n\u003Cli>USB 3.2 Link Training\u003C/li>\r\n\u003C/ul>","\u003Cp>A good understanding of USB 3.1 and prior.\u003C/p>",480,{"id":402,"name":403,"description":405,"whats_included":444,"about":404,"slug":406,"instructor_fullname":161,"instructor_email":162,"equivelent_of":21,"subscription_length":48,"price":49,"price_arbor":49,"course_category_id":19,"you_will_learn":407,"prerequisites":78,"elearning_courses":445,"reviews":446,"attachments":452,"bundles":453,"video":454,"is_active":52,"tags":462,"ebooks":463,"certificate_preview_url":464,"modules_preview_url":465,"related_items":466,"order":7,"modules":467,"release_date":114,"modules_count":67,"presentation_id":408,"presentation":804,"presentations":812,"meta_title":403,"meta_description":815,"meta_keywords":816,"evaluation_id":817,"vector_store_id":67},"\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/vt_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/vt_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PC Virtualization eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",[],[447],{"id":448,"comment":449,"elearning_course_id":402,"created_at":450,"updated_at":451},98,"\u003Cp>\u003Cspan style=\"color: rgb(224, 62, 45);\">\"Illustrative diagrams, quality audio, deep industry knowledge, technical expertise, Intel specific IO-enhancements!\"\u003C/span>\u003C/p>\n\u003Cp style=\"padding-left: 40px;\">\u003Cspan style=\"color: rgb(224, 62, 45);\">- Eric N.\u003C/span>\u003C/p>","2025-05-02T03:21:46.000000Z","2025-07-30T16:38:52.000000Z",[],[],{"id":455,"local_path":456,"file_name":457,"mime":67,"vimeo_uri":458,"duration":7,"thumbnail_filename":459,"local_thumbnail_path":460,"thumbnail_url":461},37744,"storage/app/videos/legacy/previews/","legacy-417348502.mp4","/videos/417348502","PC_Virtualization_eLearning_Course_thumbnail.png","storage/app/public/thumbnails/","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/PC_Virtualization_eLearning_Course_thumbnail.png",[],[],"https://mindshare.com/storage/images/mindshare_certificate_preview.svg","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/full_817.png",[],[468,477,485,493,501,509,516,524,532,539,547,554,562,569,577,584,592,600,607,615,623,631,638,646,653,661,668,675,683,690,697,704,711,719,726,733,740,747,754,761,768,775,783,790,797],{"id":469,"internal_title":470,"lesson_title":471,"lesson_description":472,"lesson_time":473,"test":474,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":476,"is_evaluation":67},36650,"Module 1a: Introduction to Virtualization-36650","Module 1a: Introduction to Virtualization","Covers table of contents, intro to multi-tasking, encapsulation and virtualization, application level virtualization, API virtualization, containers, emulation",27,[],88,[],{"id":478,"internal_title":479,"lesson_title":480,"lesson_description":481,"lesson_time":482,"test":483,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":484,"is_evaluation":67},36649,"Module 1b: Introduction to Virtualization-36649","Module 1b: Introduction to Virtualization","Machine (server) virtualization, Type 1 vs Type 2 hypervisors, guest vs host, virtual machine definition, partitioning, operating system vs hypervisor",29,[],[],{"id":486,"internal_title":487,"lesson_title":488,"lesson_description":489,"lesson_time":490,"test":491,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":492,"is_evaluation":67},36648,"Module 1c: Introduction to Virtualization-36648","Module 1c: Introduction to Virtualization","Everything seen by guest is fake, multiple guests, monolithic hypervisor vs microkernel, thin hypervisor, why virtualization?, consolidation, migration, virtual storage, virtual desktop",24,[],[],{"id":494,"internal_title":495,"lesson_title":496,"lesson_description":497,"lesson_time":498,"test":499,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":500,"is_evaluation":67},36647,"Module 2a: Processor Virtualization: Trap and Emulate Basics-36647","Module 2a: Processor Virtualization: Trap and Emulate Basics","Intro to trap and emulate approach, privileged instructions vs sensitive instructions, x86 register set, x86 operating modes, privilege levels, exceptions",26,[],[],{"id":502,"internal_title":503,"lesson_title":504,"lesson_description":505,"lesson_time":506,"test":507,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":508,"is_evaluation":67},36646,"Module 2b: Processor Virtualization: Trap and Emulate Basics-36646","Module 2b: Processor Virtualization: Trap and Emulate Basics","Trap and emulate examples: MMIO, PCI Config space, optimizing trap and emulate",19,[],[],{"id":510,"internal_title":511,"lesson_title":512,"lesson_description":513,"lesson_time":23,"test":514,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":515,"is_evaluation":67},36645,"Module 3a: Processor Virtualization: Software Techniques-36645","Module 3a: Processor Virtualization: Software Techniques","Ring aliasing, Flags register, paravirtualization",[],[],{"id":517,"internal_title":518,"lesson_title":519,"lesson_description":520,"lesson_time":521,"test":522,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":523,"is_evaluation":67},36644,"Module 3b: Processor Virtualization: Software Techniques-36644","Module 3b: Processor Virtualization: Software Techniques","Binary translation, VMWare and binary translation: Translation Units (TUs), Compiled Code Fragments (CCFs), user-mode exceptions and the VMM (hypervisor), adaptive binary translation, impact on memory (DRAM), processor architecture issues",30,[],[],{"id":525,"internal_title":526,"lesson_title":527,"lesson_description":528,"lesson_time":529,"test":530,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":531,"is_evaluation":67},36643,"Module 4a: Processor Virtualization: Intel VT-x-36643","Module 4a: Processor Virtualization: Intel VT-x","Terminology, new modes of operation (VMX non-root mode and VMX root mode)",20,[],[],{"id":533,"internal_title":534,"lesson_title":535,"lesson_description":536,"lesson_time":490,"test":537,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":538,"is_evaluation":67},36642,"Module 4b: Processor Virtualization: Intel VT-x-36642","Module 4b: Processor Virtualization: Intel VT-x","Enabling VMX root mode, multiple guests and multiple virtual processors, VMXON region, Virtual Machine Control Structure (VMCS)",[],[],{"id":540,"internal_title":541,"lesson_title":542,"lesson_description":543,"lesson_time":544,"test":545,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":546,"is_evaluation":67},36641,"Module 4c: Processor Virtualization: Intel VT-x-36641","Module 4c: Processor Virtualization: Intel VT-x","VMCS revision, mode switching and the VMCS, guest state area, VMResume loop and #VE",23,[],[],{"id":548,"internal_title":549,"lesson_title":550,"lesson_description":551,"lesson_time":23,"test":552,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":553,"is_evaluation":67},36640,"Module 4d: Processor Virtualization: Intel VT-x-36640","Module 4d: Processor Virtualization: Intel VT-x","Host state area, VM execution controls (pin based), NMI virtualization, preemption timer, MSR bitmaps, primary processor controls vs secondary processor",[],[],{"id":555,"internal_title":556,"lesson_title":557,"lesson_description":558,"lesson_time":559,"test":560,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":561,"is_evaluation":67},36639,"Module 4e: Processor Virtualization: Intel VT-x-36639","Module 4e: Processor Virtualization: Intel VT-x","More execution control fields, APIC virtualization and the VMCS, VM Entry controls, VM Exit controls, VM Exit information, exit reasons, accessing the VMCS (VMRead and VMWrite)",32,[],[],{"id":563,"internal_title":564,"lesson_title":565,"lesson_description":566,"lesson_time":482,"test":567,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":568,"is_evaluation":67},36638,"Module 5a: Processor Virtualization: Multi-Core and SMP Guests-36638","Module 5a: Processor Virtualization: Multi-Core and SMP Guests","VMCSs with multiple guests, multiple cores, and multiple virtual processors, SMP in the guest, processor overcommit",[],[],{"id":570,"internal_title":571,"lesson_title":572,"lesson_description":573,"lesson_time":574,"test":575,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":576,"is_evaluation":67},36637,"Module 5b: Processor Virtualization: Multi-Core and SMP Guests-36637","Module 5b: Processor Virtualization: Multi-Core and SMP Guests","Hyperthreading and VMWare, Intel-VT detection and enable, MSRs related to VMX behavior",41,[],[],{"id":578,"internal_title":579,"lesson_title":580,"lesson_description":581,"lesson_time":19,"test":582,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":583,"is_evaluation":67},36636,"Module 5c: Processor Virtualization: Multi-Core and SMP Guests-36636","Module 5c: Processor Virtualization: Multi-Core and SMP Guests","Real mode guests, system management mode (SMM), dual monitor SMM, new instructions for Intel VT",[],[],{"id":585,"internal_title":586,"lesson_title":587,"lesson_description":588,"lesson_time":589,"test":590,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":591,"is_evaluation":67},36635,"Module 6: Processor Virtualization: Nested Virtualization-36635","Module 6: Processor Virtualization: Nested Virtualization","Defines nested virtualization, terminology, different techniques to accomplish (binary translation, paravirtualization, hardware support, VMCS shadowing)",15,[],[],{"id":593,"internal_title":594,"lesson_title":595,"lesson_description":596,"lesson_time":597,"test":598,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":599,"is_evaluation":67},36634,"Module 7a: Processor Virtualization: Virtualization of Interrupts-36634","Module 7a: Processor Virtualization: Virtualization of Interrupts","Brief history of x86 interrupts, priority of vectors, 8259A behavior, APICs introduced, Local APIC, IO APIC, interrupt delivery example",25,[],[],{"id":601,"internal_title":602,"lesson_title":603,"lesson_description":604,"lesson_time":529,"test":605,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":606,"is_evaluation":67},36633,"Module 7b: Processor Virtualization: Virtualization of Interrupts-36633","Module 7b: Processor Virtualization: Virtualization of Interrupts","Masking interrupts, interrupt shadows, interrupts to guest or hypervisor, virtual vs physical interrupt, Intel event injection, Intel interruptibility states, Intel activity states, APIC virtualization, virtual APIC registers",[],[],{"id":608,"internal_title":609,"lesson_title":610,"lesson_description":611,"lesson_time":612,"test":613,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":614,"is_evaluation":67},36632,"Module 8: Processor Virtualization: Performance Observations and Other Uses-36632","Module 8: Processor Virtualization: Performance Observations and Other Uses","Overhead of classical virtualization, Intel VT performance, software vs hardware assists, biggest cause of intercepts, paravirtualization help, application wrapping, application partitioning, hypervisor call (Hypercall), other uses of virtualization",33,[],[],{"id":616,"internal_title":617,"lesson_title":618,"lesson_description":619,"lesson_time":620,"test":621,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":622,"is_evaluation":67},36631,"Module 9: Processor Virtualization: Security Features and Intel TXT-36631","Module 9: Processor Virtualization: Security Features and Intel TXT","Virtualization and security, root of trust, Trusted Platform Module (TPM), LaGrande technology, safer mode extensions, DMA protection",9,[],[],{"id":624,"internal_title":625,"lesson_title":626,"lesson_description":627,"lesson_time":628,"test":629,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":630,"is_evaluation":67},36630,"Module 10a: Memory Virtualization: x86 Memory Addressing Intro-36630","Module 10a: Memory Virtualization: x86 Memory Addressing Intro","- x86 memory addressing intro, segmentation (segmented memory model vs flat memory model), basic paging implementation, page directory entry, page table entry",31,[],[],{"id":632,"internal_title":633,"lesson_title":634,"lesson_description":635,"lesson_time":19,"test":636,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":637,"is_evaluation":67},36629,"Module 10b: Memory Virtualization: x86 Memory Addressing Intro-36629","Module 10b: Memory Virtualization: x86 Memory Addressing Intro","On-demand paging example, Page Size Extensions (PSE), 4MB pages, Physical Address Extensions (PAE), 2MB pages, IA32e (Long) mode paging, 4KB, 2MB and 1GB pages",[],[],{"id":639,"internal_title":640,"lesson_title":641,"lesson_description":642,"lesson_time":643,"test":644,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":645,"is_evaluation":67},36628,"Module 11: Memory Virtualization: Shadow Paging-36628","Module 11: Memory Virtualization: Shadow Paging","Block allocation of memory and issues with that approach, shadow paging example, building shadow page tables, maintaining shadow page tables, thrashing the TLBs, optimizations, issues with shadow page table approach",37,[],[],{"id":647,"internal_title":648,"lesson_title":649,"lesson_description":650,"lesson_time":559,"test":651,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":652,"is_evaluation":67},36627,"Module 12: Memory Virtualization: Intel Extended Page Tables (EPTs)-36627","Module 12: Memory Virtualization: Intel Extended Page Tables (EPTs)","Performance impacts of shadow paging, hardware assist for paging, Extended Page Table (EPT) implementation, EPT entries, page modification logging, TLB behavior with EPT, Virtual Processor Identifiers (VPIDs)",[],[],{"id":654,"internal_title":655,"lesson_title":656,"lesson_description":657,"lesson_time":658,"test":659,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":660,"is_evaluation":67},36626,"Module 13: Memory Virtualization: Memory Overcommit and Cache Management-36626","Module 13: Memory Virtualization: Memory Overcommit and Cache Management","Memory overcommit explanation, handling page faults within the guest, memory hot plug, balloon driver concept, page sharing, Linux and Kernel Same-page Merging (KSM)",28,[],[],{"id":662,"internal_title":663,"lesson_title":664,"lesson_description":665,"lesson_time":490,"test":666,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":667,"is_evaluation":67},36625,"Module 14a: IO Virtualization: Introduction and Approaches-36625","Module 14a: IO Virtualization: Introduction and Approaches","Explanation of why a device cannot be directly shared simultaneously between two guests, approaches for sharing, Trap and Emulation approach (pros and cons), Paravirtualization approach (pros and cons)",[],[],{"id":669,"internal_title":670,"lesson_title":671,"lesson_description":672,"lesson_time":23,"test":673,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":674,"is_evaluation":67},36624,"Module 14b: IO Virtualization: Introduction and Approaches-36624","Module 14b: IO Virtualization: Introduction and Approaches","Passthrough approach (pros and cons), PCIe Single-Root IO Virtualization (SRIOV), issues with passthrough: DMA operations and Interrupt delivery, description of DMA issue of passthrough approach, IOMMU (DMA Remapping Engine) solution, hypervisor involvement",[],[],{"id":676,"internal_title":677,"lesson_title":678,"lesson_description":679,"lesson_time":680,"test":681,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":682,"is_evaluation":67},36623,"Module 15a: IO Virtualization: Virtualization and the Network-36623","Module 15a: IO Virtualization: Virtualization and the Network","Microsoft WfW, hubs and switches, networking models, switch vs router, virtual NICs for guests, VMWare and MAC assignment",21,[],[],{"id":684,"internal_title":685,"lesson_title":686,"lesson_description":687,"lesson_time":23,"test":688,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":689,"is_evaluation":67},36622,"Module 15b: IO Virtualization: Virtualization and the Network-36622","Module 15b: IO Virtualization: Virtualization and the Network","Redundancy and teaming, multiple software switches, TCP performance issue, CPU saturation, VMWare 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logging",[],[],{"id":748,"internal_title":749,"lesson_title":750,"lesson_description":751,"lesson_time":521,"test":752,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":753,"is_evaluation":67},36613,"Module 21: IO Virtualization: Shared Virtual Memory, PCIe PASID and Intel VT-d (Part 2: VA -> [gPA ->] PA)-36613","Module 21: IO Virtualization: Shared Virtual Memory, PCIe PASID and Intel VT-d (Part 2: VA -> [gPA ->] PA)","Purpose of Shared Virtual Memory (SVM), SVM example usage and issues, Process Address Space ID (PASID) solution, PCIe TLP prefix, PASID capability structure, DMAR (IOMMU) support for PASIDs, Extended Root Entry format, Extended Context Entry format",[],[],{"id":755,"internal_title":756,"lesson_title":757,"lesson_description":758,"lesson_time":628,"test":759,"lab":67,"lesson_completed":67,"module_completed":67,"is_active":52,"module_category_id":475,"category":760,"is_evaluation":67},36612,"Module 22: IO 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src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PCIe 5.0 eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PCIe eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":5,"title":6,"created_at":831,"updated_at":832,"order":7,"vimeo_folder_id":833},{"id":364,"name":365,"about":366,"instructor_fullname":161,"instructor_email":162,"price":49,"price_arbor":49,"created_at":821,"updated_at":844,"you_will_learn":369,"equivelent_of":13,"subscription_length":48,"video_id":845,"is_active":52,"prerequisites":370,"modified_at":371,"order":9,"presentation_id":372,"slug":368,"course_category_id":5,"release_date":846,"old_product_id":847,"meta_description":848,"meta_keywords":849,"author_signature":850,"description":367,"meta_title":848,"whats_included":851,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":852},"2026-04-21T13:48:55.000000Z",37768,"2024-11-15 06:00:00",854,"PCI Express Security eLearning Course","pcie, pci express, security, ide, encryption, tutorial, elearning","Paul-Devriendt","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr 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solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":5,"title":6,"created_at":831,"updated_at":832,"order":7,"vimeo_folder_id":833},{"id":146,"name":147,"about":138,"instructor_fullname":45,"instructor_email":46,"price":150,"price_arbor":150,"created_at":821,"updated_at":854,"you_will_learn":151,"equivelent_of":13,"subscription_length":48,"video_id":855,"is_active":52,"prerequisites":152,"modified_at":153,"order":13,"presentation_id":154,"slug":149,"course_category_id":5,"release_date":856,"old_product_id":857,"meta_description":147,"meta_keywords":858,"author_signature":828,"description":148,"meta_title":147,"whats_included":859,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":860},"2026-10-22T18:55:05.000000Z",37756,"2024-11-14 06:00:00",774,"pcie tutorial, 128b/130b","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" 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modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PCIe eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":5,"title":6,"created_at":831,"updated_at":832,"order":7,"vimeo_folder_id":833},{"id":70,"name":71,"about":72,"instructor_fullname":75,"instructor_email":76,"price":49,"price_arbor":49,"created_at":821,"updated_at":862,"you_will_learn":77,"equivelent_of":13,"subscription_length":48,"video_id":863,"is_active":52,"prerequisites":78,"modified_at":79,"order":21,"presentation_id":80,"slug":74,"course_category_id":5,"release_date":864,"old_product_id":865,"meta_description":866,"meta_keywords":866,"author_signature":840,"description":73,"meta_title":71,"whats_included":867,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":868},"2026-10-22T16:26:43.000000Z",37761,"2024-11-16 06:00:00",808,"pcie, pci express, elearning, online training","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pciecore_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pciecore_slides.png\" alt=\"PDF of course slides\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pcie3_cover_ds.png\" alt=\"img\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" 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resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":5,"title":6,"created_at":831,"updated_at":832,"order":7,"vimeo_folder_id":833},{"id":136,"name":137,"about":138,"instructor_fullname":75,"instructor_email":76,"price":141,"price_arbor":141,"created_at":821,"updated_at":870,"you_will_learn":142,"equivelent_of":11,"subscription_length":48,"video_id":871,"is_active":52,"prerequisites":78,"modified_at":143,"order":25,"presentation_id":144,"slug":140,"course_category_id":5,"release_date":846,"old_product_id":872,"meta_description":873,"meta_keywords":874,"author_signature":840,"description":139,"meta_title":137,"whats_included":875,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":876},"2025-07-30T15:53:16.000000Z",37716,248,"mindshare pci express fundamentals elearning","pci express, pcie, elearning, module, tutorial, training, online, on-demand, self-paced","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pciefund_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pciefund_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PCIe Fundamentals eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":5,"title":6,"created_at":831,"updated_at":832,"order":7,"vimeo_folder_id":833},{"id":175,"name":176,"about":177,"instructor_fullname":75,"instructor_email":76,"price":64,"price_arbor":64,"created_at":821,"updated_at":878,"you_will_learn":180,"equivelent_of":11,"subscription_length":48,"video_id":879,"is_active":52,"prerequisites":181,"modified_at":67,"order":28,"presentation_id":154,"slug":179,"course_category_id":5,"release_date":846,"old_product_id":880,"meta_description":881,"meta_keywords":882,"author_signature":840,"description":178,"meta_title":883,"whats_included":884,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":885},"2025-10-31T13:14:21.000000Z",37754,762,"PIPE - Physical Interface for PCI Express and more","PIPE, pcie, usb4, thunderbolt, sata, displayport, eLearning","PIPE 6.0 eLearning Course","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pipe2020_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pipe2020_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PCIe PIPE 6.0 eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":5,"title":6,"created_at":831,"updated_at":832,"order":7,"vimeo_folder_id":833},[887,899,908,914],{"id":116,"name":117,"about":118,"instructor_fullname":88,"instructor_email":89,"price":49,"price_arbor":49,"created_at":821,"updated_at":888,"you_will_learn":121,"equivelent_of":13,"subscription_length":48,"video_id":889,"is_active":52,"prerequisites":122,"modified_at":123,"order":7,"presentation_id":124,"slug":120,"course_category_id":9,"release_date":846,"old_product_id":890,"meta_description":891,"meta_keywords":892,"author_signature":893,"description":119,"meta_title":894,"whats_included":895,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":896},"2025-10-31T13:16:58.000000Z",37769,861,"CXL 3.1 Update eLearning, compute express link","cxl 3.1, tutorial, training, online","Ravi-Budruk","CXL 3.1 Update eLearning","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr 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style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":9,"title":10,"created_at":897,"updated_at":898,"order":11,"vimeo_folder_id":67},"2023-04-19T13:09:15.000000Z","2024-10-15T12:09:31.000000Z",{"id":95,"name":96,"about":97,"instructor_fullname":88,"instructor_email":89,"price":100,"price_arbor":100,"created_at":821,"updated_at":900,"you_will_learn":101,"equivelent_of":25,"subscription_length":48,"video_id":901,"is_active":52,"prerequisites":102,"modified_at":103,"order":11,"presentation_id":104,"slug":99,"course_category_id":9,"release_date":846,"old_product_id":902,"meta_description":903,"meta_keywords":904,"author_signature":893,"description":98,"meta_title":905,"whats_included":906,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":907},"2025-10-31T13:15:59.000000Z",37764,831,"Comprehensive CXL 2.0 eLearning","cxl, compute express link, elearning, training","CXL 2.0 eLearning","\u003Ctable border=\"0\" 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days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":9,"title":10,"created_at":897,"updated_at":898,"order":11,"vimeo_folder_id":67},{"id":83,"name":84,"about":85,"instructor_fullname":88,"instructor_email":89,"price":90,"price_arbor":90,"created_at":821,"updated_at":909,"you_will_learn":91,"equivelent_of":11,"subscription_length":48,"video_id":910,"is_active":52,"prerequisites":51,"modified_at":92,"order":9,"presentation_id":93,"slug":87,"course_category_id":9,"release_date":846,"old_product_id":911,"meta_description":84,"meta_keywords":904,"author_signature":893,"description":86,"meta_title":84,"whats_included":912,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":913},"2025-10-31T13:15:28.000000Z",37762,824,"\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/cxlfund_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/cxlfund_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>CXL Fundamentals eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":9,"title":10,"created_at":897,"updated_at":898,"order":11,"vimeo_folder_id":67},{"id":374,"name":375,"about":376,"instructor_fullname":88,"instructor_email":89,"price":90,"price_arbor":188,"created_at":915,"updated_at":916,"you_will_learn":379,"equivelent_of":9,"subscription_length":48,"video_id":917,"is_active":52,"prerequisites":380,"modified_at":381,"order":13,"presentation_id":67,"slug":378,"course_category_id":9,"release_date":918,"old_product_id":67,"meta_description":919,"meta_keywords":920,"author_signature":893,"description":377,"meta_title":921,"whats_included":922,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":923},"2026-05-23T13:05:02.000000Z","2026-06-04T15:50:43.000000Z",39355,"2026-05-23 05:00:00","ucie eLearning","ucie, universal chiplet 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modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":9,"title":10,"created_at":897,"updated_at":898,"order":11,"vimeo_folder_id":67},[925,935,943,951,959],{"id":270,"name":271,"about":272,"instructor_fullname":45,"instructor_email":46,"price":49,"price_arbor":49,"created_at":821,"updated_at":926,"you_will_learn":275,"equivelent_of":21,"subscription_length":48,"video_id":927,"is_active":52,"prerequisites":276,"modified_at":277,"order":7,"presentation_id":278,"slug":274,"course_category_id":13,"release_date":856,"old_product_id":928,"meta_description":929,"meta_keywords":930,"author_signature":828,"description":273,"meta_title":271,"whats_included":931,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":932},"2025-10-31T13:14:54.000000Z",37757,796,"USB4 Architecture eLearning","USB4, USB 4.0, training, tutorial, eLearning, online","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usb4_modules.png\" alt=\"PCIe Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usb4_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usb3_front_ds_130x145.jpg\" alt=\"PCIe eBook\" width=\"131\" height=\"146\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB4 Architecture eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB 3.0 eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":13,"title":14,"created_at":897,"updated_at":933,"order":9,"vimeo_folder_id":934},"2025-07-30T12:06:31.000000Z",26122208,{"id":322,"name":323,"about":324,"instructor_fullname":62,"instructor_email":63,"price":266,"price_arbor":266,"created_at":821,"updated_at":936,"you_will_learn":327,"equivelent_of":11,"subscription_length":48,"video_id":937,"is_active":52,"prerequisites":51,"modified_at":67,"order":11,"presentation_id":328,"slug":326,"course_category_id":13,"release_date":856,"old_product_id":938,"meta_description":323,"meta_keywords":939,"author_signature":940,"description":325,"meta_title":323,"whats_included":941,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":942},"2025-10-31T13:11:08.000000Z",37736,617,"usb type-c, power delivery, elearning, training, tutorial","Jay-Trodden","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usbtypec_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usbtypec_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB Type-C eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":13,"title":14,"created_at":897,"updated_at":933,"order":9,"vimeo_folder_id":934},{"id":435,"name":436,"about":437,"instructor_fullname":62,"instructor_email":63,"price":64,"price_arbor":64,"created_at":821,"updated_at":944,"you_will_learn":440,"equivelent_of":11,"subscription_length":48,"video_id":945,"is_active":52,"prerequisites":441,"modified_at":67,"order":9,"presentation_id":442,"slug":439,"course_category_id":13,"release_date":856,"old_product_id":946,"meta_description":947,"meta_keywords":948,"author_signature":940,"description":438,"meta_title":436,"whats_included":949,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":950},"2025-10-31T13:13:03.000000Z",37748,706,"USB 3.2 Update","usb 3.2, ssp, eLearning, training, tutorial","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usb32up_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usb32up_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB 3.2 Update eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":13,"title":14,"created_at":897,"updated_at":933,"order":9,"vimeo_folder_id":934},{"id":224,"name":225,"about":226,"instructor_fullname":229,"instructor_email":230,"price":150,"price_arbor":150,"created_at":821,"updated_at":952,"you_will_learn":231,"equivelent_of":13,"subscription_length":48,"video_id":953,"is_active":52,"prerequisites":78,"modified_at":67,"order":13,"presentation_id":232,"slug":228,"course_category_id":13,"release_date":846,"old_product_id":954,"meta_description":225,"meta_keywords":955,"author_signature":956,"description":227,"meta_title":225,"whats_included":957,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":958},"2025-10-31T13:12:07.000000Z",37743,674,"usb training, elearning, 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src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB 3.1 eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB 3.0 eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":13,"title":14,"created_at":897,"updated_at":933,"order":9,"vimeo_folder_id":934},{"id":57,"name":58,"about":59,"instructor_fullname":62,"instructor_email":63,"price":64,"price_arbor":64,"created_at":821,"updated_at":960,"you_will_learn":65,"equivelent_of":11,"subscription_length":48,"video_id":961,"is_active":52,"prerequisites":66,"modified_at":67,"order":21,"presentation_id":68,"slug":61,"course_category_id":13,"release_date":846,"old_product_id":962,"meta_description":963,"meta_keywords":964,"author_signature":940,"description":60,"meta_title":58,"whats_included":965,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":966},"2025-10-31T13:10:47.000000Z",37725,542,"xHCI eLearning course","xhci, training, eLearning, tutorial, mindshare, extensible host controller","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/xhci_modules.png\" alt=\"PCIe Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/xhci_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/usb3_front_ds_130x145.jpg\" alt=\"PCIe eBook\" width=\"131\" height=\"146\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>xHCI eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB 3.0 eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":13,"title":14,"created_at":897,"updated_at":933,"order":9,"vimeo_folder_id":934},[968,981,990,997],{"id":243,"name":244,"about":245,"instructor_fullname":198,"instructor_email":199,"price":100,"price_arbor":188,"created_at":969,"updated_at":970,"you_will_learn":248,"equivelent_of":21,"subscription_length":48,"video_id":971,"is_active":52,"prerequisites":249,"modified_at":250,"order":7,"presentation_id":67,"slug":247,"course_category_id":16,"release_date":972,"old_product_id":67,"meta_description":973,"meta_keywords":974,"author_signature":975,"description":246,"meta_title":244,"whats_included":976,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":977},"2025-12-05T15:33:22.000000Z","2026-02-02T20:43:06.000000Z",39245,"2026-02-01 06:00:00","high bandwidth memory elearning","hbm, hbm4, hbm3, hbm4e","John-Swindle","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/hbm_modules.png\" alt=\"Modules\" width=\"190\" height=\"130\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/hbm_slides.png\" alt=\"img\" width=\"175\" height=\"112\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>HBM eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" 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style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your 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resume/CV)\u003C/p>\r\n\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":19,"title":20,"created_at":1009,"updated_at":1010,"order":21,"vimeo_folder_id":67},{"id":40,"name":41,"about":42,"instructor_fullname":45,"instructor_email":46,"price":49,"price_arbor":49,"created_at":821,"updated_at":1006,"you_will_learn":50,"equivelent_of":47,"subscription_length":48,"video_id":1022,"is_active":52,"prerequisites":51,"modified_at":53,"order":9,"presentation_id":54,"slug":44,"course_category_id":19,"release_date":846,"old_product_id":1023,"meta_description":1024,"meta_keywords":1025,"author_signature":828,"description":43,"meta_title":41,"whats_included":1026,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":1027},37750,718,"IO Virtualization for Intel Platforms","Intel VT-d, virtualization, PCIe SRIOV","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/iovintel_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/iovintel_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>IOV Intel eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":19,"title":20,"created_at":1009,"updated_at":1010,"order":21,"vimeo_folder_id":67},[1029,1041,1050,1058,1065,1072,1078],{"id":347,"name":348,"about":349,"instructor_fullname":75,"instructor_email":76,"price":100,"price_arbor":188,"created_at":1030,"updated_at":1031,"you_will_learn":352,"equivelent_of":21,"subscription_length":48,"video_id":1032,"is_active":52,"prerequisites":51,"modified_at":353,"order":7,"presentation_id":67,"slug":351,"course_category_id":23,"release_date":972,"old_product_id":67,"meta_description":1033,"meta_keywords":1034,"author_signature":840,"description":350,"meta_title":1035,"whats_included":1036,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":1037},"2025-12-07T22:05:34.000000Z","2026-02-03T16:08:29.000000Z",39247,"nvme elearning","nvme 2.3, online training, eLearning","NVMe 2.x eLearning course","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/nvme2x_modules.png\" alt=\"NVMe Modules\" width=\"233\" height=\"160\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/nvme2x_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"231\" height=\"160\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pcie3_cover_ds.png\" alt=\"PCIe eBook\" width=\"125\" height=\"155\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>NVMe 2.x eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PCI Express eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>Purchasing this NVMe 2.x eLearning course will provide the materials shown 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src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>SAS 3.0 eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>SAS eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",{"id":23,"title":24,"created_at":1038,"updated_at":1039,"order":25,"vimeo_folder_id":1040},{"id":280,"name":281,"about":282,"instructor_fullname":75,"instructor_email":76,"price":285,"price_arbor":285,"created_at":821,"updated_at":1066,"you_will_learn":286,"equivelent_of":13,"subscription_length":48,"video_id":1073,"is_active":52,"prerequisites":240,"modified_at":67,"order":25,"presentation_id":287,"slug":284,"course_category_id":23,"release_date":846,"old_product_id":372,"meta_description":1074,"meta_keywords":1075,"author_signature":840,"description":283,"meta_title":1074,"whats_included":1076,"evaluation_id":817,"vector_store_id":67,"ai_assistant_id":67,"category":1077},37724,"Serial ATA eLearning course","serial ata, sata, elearning, mindshare, online, training","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/sata3_modules.png\" alt=\"PCIe Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/sata3_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/sata_ebook.jpg\" alt=\"PCIe eBook\" width=\"130\" height=\"145\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>SATA 3.2 eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>SATA eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / 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233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your 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