PIPE 6.0 enables the development of PHYs for PCI Express, SATA, USB, DisplayPort, and USB4. Such PIPE compliant PHYs can be delivered as standalone ICs or as macrocell IPs for inclusion in ASICs. The course describes a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. Two independently designed PHY and MAC ASICs/macrocell IPs will connect and work together as long as they meet the design requirements of PIPE 6.0. This course does not describe the internal design of a compliant PHY chip or higher layer protocol architecture. To understand PCIe, SATA or USB architecture, you would need to take one of MindShare’s other comprehensive architecture courses.

The course covers PIPE interface operational behavior in PCIe, USB and SATA modes. Additionally, you will also learn the signaling protocol associated with the Link Training process, Equalization process and Lane Margining.