[{"data":1,"prerenderedAt":95},["ShallowReactive",2],{"GET-live-training-course/slug/arm-64-bit-architecture-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":16,"course_outline":17,"supplied_materials":16,"thumbnail":18,"elearning_courses":19,"ebooks":47,"topics":48,"reviews":94,"meta_title":16,"meta_description":16,"meta_keywords":16},696,"ARMv8-A and v9-A 64-bit Architecture","arm-64-bit-architecture","\u003Cp>This course covers the 64-bit ARMv8-A architecture that follows on from and offers compatibility with the earlier ARMv7-A 32-bit architecture. Examples of processors that first implemented this 64-bit architecture are the ARM Cortex-A53 and Cortex A57 processors. Since the successful introduction of the ARMv8-A architecture and products, there have been several architectural enhancements. This course includes enhancements 8.1, 8.2, 8.3, 8.4, 8.5 and 8.6. This course also covers the additions in v9-A architecture. This course concentrates on the ISA – Instruction Set Architecture, rather than the details of individual implementations.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp class=\"sectionsubhead\">\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARMv8-A and ARMv9-A 64-bit Architecture\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli>PDF of course slides\u003C/li>\r\n\u003C/ul>","\u003Cul>\r\n\u003Cli>ARM architecture (ARMv8.x-A and ARMv9.x-A)\u003C/li>\r\n\u003Cli>Support for execution of 32-bit ARMv7-A code\u003C/li>\r\n\u003Cli>64-bit ISA (registers, instruction set, system instructions, etc)\u003C/li>\r\n\u003Cli>Floating point and Neon\u003C/li>\r\n\u003Cli>Calling conventions\u003C/li>\r\n\u003Cli>Memory model and paging\u003C/li>\r\n\u003Cli>Exception and Interrupt handling, and the exception levels\u003C/li>\r\n\u003Cli>Exception Level 2, intended for virtualization support\u003C/li>\r\n\u003Cli>TrustZone overview (Secure monitor at Exception Level 3 plus secure world)\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003Cli>Debug\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cem>Note: v8-A includes compatibility support for v7-A code execution. This support is covered, but not the details of the v7-A architecture.\u003C/em>\u003C/p>","\u003Cp>Knowledge of ARMv7 32-bit Architecture and general computer architecture is recommended.\u003C/p>",true,3,"4 or 5 days",null,"\u003Cul>\r\n                \u003Cli>Introduction to ARM 64-bit Architecture\u003C/li>\r\n                \u003Cli>ARM architecture profiles, what is v8-A and the other architecture profiles\u003C/li>\r\n                \u003Cli>ARM architecture extensions to v8-A, the v8.1A, v8.2-A, etc and v9-A\u003C/li>\r\n                \u003Cli>v8-A introduction and rational\u003C/li>\r\n                \u003Cli>Support for v7 legacy code\r\n                \u003Cul>\r\n                    \u003Cli>AArch32 and AArch64 state\u003C/li>\r\n                    \u003Cli>v7 instruction set changes\r\n                    \u003Cul>\r\n                        \u003Cli>Deprecation\u003C/li>\r\n                        \u003Cli>Additional features (some new 64-bit features have also been added as new features available to 32-bit execution)\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>64-bit platform architecture overview\r\n                \u003Cul>\r\n                    \u003Cli>Sample SoC\u003C/li>\r\n                    \u003Cli>MP Core\u003C/li>\r\n                    \u003Cli>Interconnect (ACE or CHI)\r\n                    \u003Cul>\r\n                        \u003Cli>Coherency and the interconnect\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Distributed interrupt controller\u003C/li>\r\n                    \u003Cli>Role of firmware\u003C/li>\r\n                    \u003Cli>Booting\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>A64 ISA\u003C/li>\r\n                \u003Cli>Integer registers\u003C/li>\r\n                \u003Cli>Instruction set\r\n                \u003Cul>\r\n                    \u003Cli>Integer operations\u003C/li>\r\n                    \u003Cli>Memory operations\u003C/li>\r\n                    \u003Cli>Stack\u003C/li>\r\n                    \u003Cli>System instructions\r\n                    \u003Cul>\r\n                        \u003Cli>System control registers\u003C/li>\r\n                        \u003Cli>Relationship to v7 support and co-processors\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Calling conventions\u003C/li>\r\n                    \u003Cli>Memory access (DRAM and device)\r\n                    \u003Cul>\r\n                        \u003Cli>Ordering model\u003C/li>\r\n                        \u003Cli>Barriers\r\n                        \u003Cul>\r\n                            \u003Cli>dmb, dsb, isb\u003C/li>\r\n                            \u003Cli>load-acquire and store-release\u003C/li>\r\n                            \u003Cli>Domains\u003C/li>\r\n                        \u003C/ul>\r\n                        \u003C/li>\r\n                        \u003Cli>Semaphores\u003C/li>\r\n                        \u003Cli>Cache management\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Floating point, advanced SIMD, crypto\r\n                    \u003Cul>\r\n                        \u003Cli>Registers and instructions\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Exception levels\r\n                    \u003Cul>\r\n                        \u003Cli>The 4 exception levels\u003C/li>\r\n                        \u003Cli>Stack model, handler and thread\u003C/li>\r\n                        \u003Cli>Vector table\u003C/li>\r\n                        \u003Cli>Core implementation choices\u003C/li>\r\n                        \u003Cli>Switching AArch32 and AArch64 state\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Exception and interrupt handling\r\n                    \u003Cul>\r\n                        \u003Cli>Control of delivery of exceptions and interrupts\u003C/li>\r\n                        \u003Cli>Syndrome registers\u003C/li>\r\n                        \u003Cli>Switching exception levels\u003C/li>\r\n                        \u003Cli>Return from exception\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Paging\r\n                    \u003Cul>\r\n                        \u003Cli>Memory management with page tables\u003C/li>\r\n                        \u003Cli>4K, 16K and 64K granules\u003C/li>\r\n                        \u003Cli>Page sizes\u003C/li>\r\n                        \u003Cli>Features achieved with page tables, such as execute never\u003C/li>\r\n                        \u003Cli>Address space trickery – fields in pointers that are not part of the address, such as tags and pointer authentication\u003C/li>\r\n                        \u003Cli>TLB management\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>EL2 Overview\r\n                \u003Cul>\r\n                    \u003Cli>Processor features intended for virtualization\u003C/li>\r\n                    \u003Cli>Use of exception levels\u003C/li>\r\n                    \u003Cli>Memory management\r\n                    \u003Cul>\r\n                        \u003Cli>Second level page tables\u003C/li>\r\n                        \u003Cli>Memory partitioning\u003C/li>\r\n                        \u003Cli>I/O MMU (SMMU)\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>The use of EL2 for UEFI execution during boot\u003C/li>\r\n                    \u003Cli>Addition of Secure EL2 to the architecture\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Caches\r\n                \u003Cul>\r\n                    \u003Cli>Hardware cache coherency\u003C/li>\r\n                    \u003Cli>Software responsibilities\u003C/li>\r\n                    \u003Cli>Cache control in software\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Security (TrustZone)\r\n                \u003Cul>\r\n                    \u003Cli>TrustZone functionality\u003C/li>\r\n                    \u003Cli>Secure memory\u003C/li>\r\n                    \u003Cli>Links to TrustZone in other architectures\u003C/li>\r\n                    \u003Cli>32-bit or 64-bit TrustZone\u003C/li>\r\n                    \u003Cli>Implications on exception levels, and the addition of secure EL2\u003C/li>\r\n                    \u003Cli>Switching bitness of TrustZone\u003C/li>\r\n                    \u003Cli>Dynamic TrustZone, also called Realms, part of ARM’s Confidential Compute Architecture\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Other topics\r\n                \u003Cul>\r\n                    \u003Cli>Core power management, external power controller\r\n                    \u003Cul>\r\n                        \u003Cli>Power modes (dormant, shutdown)\u003C/li>\r\n                        \u003Cli>WFI, WFE, SEV\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Debug (hardware and software based debug)\u003C/li>\r\n                    \u003Cli>RAS – Reliability, Availability, Serviceability\u003C/li>\r\n                    \u003Cli>Boot process\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n            \u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_696_thumbnail_1748360436.png",[20],{"id":21,"name":22,"slug":23,"description":24,"whats_included":25,"about":26,"instructor_fullname":27,"instructor_email":28,"equivelent_of":29,"subscription_length":30,"price":31,"price_arbor":31,"course_category_id":32,"elearning_courses":33,"you_will_learn":34,"prerequisites":35,"is_active":13,"modified_at":16,"order":36,"modules_count":37,"video":38},1720,"ARM 64-bit Architecture (ARM v8-A) eLearning Course","arm-64-bit-architecture-arm-v8-a-elearning-course","\u003Cp>This course covers the 64-bit ARMv8-A architecture that follows on from and offers compatibility with the earlier ARMv7-A 32-bit architecture. Examples of processors that first implemented this 64-bit architecture are the ARM Cortex-A53 and Cortex A57 processors. Since the successful introduction of the ARMv8-A architecture and products, there have been several architectural enhancements. \u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/armv8a_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/armv8a_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>ARMv8-A eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"ARMv8-A\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","Paul Devriendt","paul@mindshare.com",4,120,"895",5,[],"\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>ARM architecture (ARMv8-A)\u003C/li>\r\n\u003Cli>Support for execution of 32-bit ARMv7-A code\u003C/li>\r\n\u003Cli>64-bit ISA (registers, instruction set, system instructions, etc)\u003C/li>\r\n\u003Cli>Floating point and Neon\u003C/li>\r\n\u003Cli>Calling conventions\u003C/li>\r\n\u003Cli>Memory and paging\u003C/li>\r\n\u003Cli>Exception and Interrupt handling, and the exception levels\u003C/li>\r\n\u003Cli>Virtualization (Exception Level 2)\u003C/li>\r\n\u003Cli>TrustZone overview (Exception Level 3)\u003C/li>\r\n\u003Cli>Power management\u003C/li>\r\n\u003Cli>Debug\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","null",30,22,{"id":39,"local_path":40,"file_name":41,"mime":16,"vimeo_uri":42,"duration":43,"thumbnail_filename":44,"local_thumbnail_path":45,"thumbnail_url":46},37726,"storage/app/videos/legacy/previews/","legacy-417348333.mp4","/videos/417348333",0,"ARM_64-bit_Architecture_(ARM_v8-A)_eLearning_Course_thumbnail.png","storage/app/public/thumbnails/","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/ARM_64-bit_Architecture_%28ARM_v8-A%29_eLearning_Course_thumbnail.png",[],[49,57,63,72,81,87],{"id":50,"course_name":51,"classroom_info":15,"virtual_classroom_info":52,"file_url":53,"course_link":54,"link":55,"file_name":56},155,"ARMv8-A and ARMv9-A 64-bit Architecture","8 or 10 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_ARMv8A_ARMv9A_64bit_Agenda.pdf","/live-training-course/arm-64-bit-architecture","/elearning-course/arm-64-bit-architecture-arm-v8-a-elearning-course","MindShare_ARMv8A_ARMv9A_64bit_Agenda.pdf",{"id":58,"course_name":59,"classroom_info":16,"virtual_classroom_info":16,"file_url":60,"course_link":16,"link":61,"file_name":62},209,"Fundamentals of ARMv8-A","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_CHANGEME_Agenda.pdf","/elearning-course/fundamentals-of-armv8-a-elearning-course","MindShare_CHANGEME_Agenda.pdf",{"id":64,"course_name":65,"classroom_info":66,"virtual_classroom_info":67,"file_url":68,"course_link":69,"link":70,"file_name":71},148,"ARMv7-A and v8-A Architecture","4 days","8 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_ARM_v7A-v8A_Outline.pdf","/live-training-course/armv7a-v8a-architecture","/elearning-course/comprehensive-arm-architecture-elearning-course","MindShare_ARM_v7A-v8A_Outline.pdf",{"id":73,"course_name":74,"classroom_info":75,"virtual_classroom_info":76,"file_url":77,"course_link":78,"link":79,"file_name":80},146,"ARMv7 32-bit Architecture","3 days","6 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_ARMv7_32bit_Architecture.pdf","/live-training-course/armv7-32-bit-architecture","/elearning-course/arm-32-bit-architecture-arm-v7-elearning-course","MindShare_ARMv7_32bit_Architecture.pdf",{"id":82,"course_name":83,"classroom_info":16,"virtual_classroom_info":16,"file_url":84,"course_link":16,"link":85,"file_name":86},164,"Fundamentals of ARM Architecture","","/elearning-course/fundamentals-of-arm-architecture","IMPORTED",{"id":88,"course_name":89,"classroom_info":75,"virtual_classroom_info":76,"file_url":90,"course_link":91,"link":92,"file_name":93},150,"ARM MCU Architecture","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_ARM_MCU_Architecture.pdf","/live-training-course/arm-mcu-architecture","/elearning-course/arm-mcu-architecture-elearning-course","MindShare_ARM_MCU_Architecture.pdf",[16],1793031959726]