[{"data":1,"prerenderedAt":117},["ShallowReactive",2],{"GET-live-training-course/slug/dram-ddr5lpddr5-architecture-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":16,"course_outline":17,"supplied_materials":16,"thumbnail":18,"elearning_courses":19,"ebooks":86,"topics":87,"reviews":113,"meta_title":114,"meta_description":115,"meta_keywords":116},725,"DRAM (DDR5/LPDDR6) Architecture","dram-ddr5lpddr5-architecture","\u003Cp class=\"MsoNormal\" style=\"margin-bottom: 0in; line-height: normal; mso-hyphenate: none;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Whether you are new to DRAM or an industry veteran seeking the latest and greatest standards, you will learn more than you expect from MindShare's DRAM courses. You may be well-versed on modern serial protocols but learning parallel-bus protocols of DDR DRAM will be valuable. You might have worked extensively with mainstream PC DRAMs and now you need to learn low-power LP DRAM designs. This DRAM course will help you design, develop, validate, verify, test, debug or support DRAM interfaces.\u003C/span>\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42); font-size: 10pt;\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp class=\"sectionsubhead\">\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"DRAM Architecture\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli style=\"font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-family: helvetica, arial, sans-serif; font-size: 10pt;\">PDF of course slides\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Ca href=\"../../elearning-course/modern-dram-ddr5-ddr4-lpddr5-lpddr4-elearning-course\">Modern DRAM eLearning Course\u003C/a>\u003C/span>\u003C/li>\r\n\u003C/ul>","\u003Cul style=\"margin-top: 0in;\" type=\"disc\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Where JEDEC expects DRAM to appear in a system\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">How a DRAM cell is addressed by the controller\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Difference between Banks, Bank Groups and Ranks\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Why the DRAM controller is so complicated\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Activation, Precharge and Refresh including newer forms\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 as fundamental technology\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Types of DIMMs\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Fly-By Routing\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5, LPDDR5 and LPDDR6 pin definitions, bank state diagrams and timing waveforms\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5 DIMM PMIC\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Dynamic Voltage and Frequency Scaling (DVFS), Frequency Set Points (FSP) and clock throttling\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">On-Die Termination (ODT)\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">JEDEC Initialization and Mode Registers\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Calibration and training\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Sources of errors and JEDEC features for handling errors\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Test philosophy and JEDEC features to assist with testing\u003C/span>\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cspan style=\"font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"line-height: 115%;\">A basic understanding of \u003C/span>\u003Cspan style=\"line-height: 115%; color: rgb(48, 51, 48); letter-spacing: 0.2pt;\">digital design and some computer architecture background\u003C/span>\u003Cspan style=\"line-height: 115%;\">.\u003C/span>\u003C/span>\u003C/p>",true,4,"4 days",null,"\u003Cul style=\"margin-top: 0in;\" type=\"disc\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">System Architecture \u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">PC Platform Architecture\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">NUMA Architecture\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">SoC Architecture\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Back to the Future DRAM Intro \u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">It's more similar than it is different\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DRAM Cell Architecture\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Problems of Activation, Precharge and Refresh\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DRAM Device Architecture \u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">SDRAM through DDR5 and LPDDR6\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Bank Groups\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR5 Bank Group options\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Packaging\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Monolithic\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Stacked Die\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">3DS, Hybrid Memory Cube, High Bandwidth Memory (HBM)\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Package-on-Package\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Dual LPDDR4 Channels\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DRAM Controller Basics\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Functional Blocks\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Address Translation/Address Mapping Examples\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Device and Dual In-line Memory Module (DIMM) Pin Descriptions\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DIMM\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Introduction to DIMM Architecture\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">UDIMM\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">RDIMM\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LRDIMM\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Fly-by Routing\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Bank State Machines, Commands, Waveforms\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Refresh\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Auto Refresh\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Self Refresh\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Auto Self Refresh\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Rowhammer Mitigations\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Target Row Refresh\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Refresh Management\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Per-Row Activation Count\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Device and DIMM Pin Descriptions\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DIMM\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR5\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR6\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 and DDR5 DIMM Architecture\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">UDIMM\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">RDIMM\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LRDIMM\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">PMIC\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 On-DIMM Address Mirroring\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5 Mirroring\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Bank State Machines, Commands, Waveforms\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR5 and LPDDR6\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Newer Forms of Refresh\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Per-Bank and Fine Granularity Refresh\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Temperature Compensated Refresh\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Self-Refresh Abort, Fast Exit\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Electrical Specifications \u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4/DDR5 POD\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR5/LPDDR6 LVSTL\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">IDD Specifications, Example\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-family: helvetica, arial, sans-serif; font-size: 10pt;\">Power Management\u003C/span>\u003C/li>\r\n\u003Cli style=\"list-style-type: none; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Power Down and Self Refresh\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4/DDR5 Max Power Saving Mode\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR5/LPDDR6 Frequency Setpoints (FSP)\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR5/LPDDR6 Dynamic Voltage and Frequency Scaling\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"square\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DVFSC, DVFSH, DVFSL, DVFSB, DVFSQ\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Introduction to Signal Integrity Issues\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Sources and Solutions\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">On-Die Termination\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Sync/Async ODT\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4/DDR5/LPDDR6 Dynamic ODT\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Data Group ODT and Command Bus ODT\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4/DDR5/LP DRAM Park Mode\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Command Bus ODT\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Initialization, Calibration and Training\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">JEDEC Initialization\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"square\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 Mode Registers\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 Initialization\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5, LPDDR5, LPDDR6 Initialization\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Calibration and Training \u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"square\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">ZQ Calibration\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Vref Training\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">CS Training Mode\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">CA Command Bus Training\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Write Leveling\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Read Calibration\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Write Calibration\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"square\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Duty Cycle Adjustment, Duty Cycle Monitor, DFE, FIFO, DQS Oscillator\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Errors and Error Handling \u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Sources of Errors\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DIMM ECC\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">On-Die ECC\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DIMM Parity\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 CA Parity\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 Write CRC\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5 Read/Write CRC\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR5/LPDDR6 Link ECC/EDC\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR6 In-line ECC with System Metadata Carve Out\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Post Package Repair\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Testing\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DRAM Functional Tests\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Structural Test Example\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Cell Test Example\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DRAM Parametric (pin) Tests\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR4 Connectivity Test Mode\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">DDR5 Loopback Mode\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">LPDDR6 Loopback Mode\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">Optional Topics\u003C/span>\r\n\u003Cul style=\"margin-top: 0in;\" type=\"circle\">\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">SMBus Overview, I3C\u003C/span>\u003C/li>\r\n\u003Cli class=\"MsoNormal\" style=\"color: black; margin-top: 0.1pt; margin-bottom: 0.1pt; line-height: normal; font-family: helvetica, arial, sans-serif; font-size: 10pt;\">\u003Cspan style=\"font-size: 10pt; font-family: helvetica, arial, sans-serif;\">NVM Transaction Overview\u003C/span>\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_725_thumbnail_1747668679.png",[20,48,70],{"id":21,"name":22,"slug":23,"description":24,"whats_included":25,"about":26,"instructor_fullname":27,"instructor_email":28,"equivelent_of":29,"subscription_length":30,"price":31,"price_arbor":31,"course_category_id":32,"elearning_courses":33,"you_will_learn":34,"prerequisites":35,"is_active":13,"modified_at":36,"order":37,"modules_count":38,"video":39},1759,"I3C Architecture eLearning Course","i3c-architecture-elearning-course","\u003Cp>This MindShare course is designed for hardware/software engineers and others needing detailed coverage of MIPI I3C protocol. \u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/i3c_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/i3c_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>I3C eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"I3C\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","Jay Trodden","elearning@mindshare.com",3,120,"595",22,[],"\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Major features defined in the MIPI I3C Basic Specification\u003C/li>\r\n\u003Cli>How MIPI I3C addresses some of the long-standing speed, power, and pin count limitations of alternative IC communication protocols, including I2C and SPI\u003C/li>\r\n\u003Cli>Why I3C devices dynamically switch data drivers between push-pull and open drain signaling\u003C/li>\r\n\u003Cli>The motivations for MIPI I3C Hot-Join in power sensitive applications\u003C/li>\r\n\u003Cli>How I3C compliant devices report bus and internal characteristics to software\u003C/li>\r\n\u003Cli>How an enhanced set of direct and broadcast Common Command Code (CCC) transactions help simplify initialization, changing bus modes, and with device control and status operations\u003C/li>\r\n\u003Cli>The use of I3C in-band interrupts (IBI) to reduce pin count and enable devices to send critical status information as part of the IBI payload.\u003C/li>\r\n\u003Cli>Key features of the MIPI I3C Host Controller Interface (HCI) Specification\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>None\u003C/p>","2025-01-02 17:08:27",2,42,{"id":40,"local_path":41,"file_name":42,"mime":16,"vimeo_uri":43,"duration":44,"thumbnail_filename":45,"local_thumbnail_path":46,"thumbnail_url":47},37765,"storage/app/videos/legacy/previews/","legacy-781539032.mp4","/videos/781539032",503,"I3C_Architecture_eLearning_Course_thumbnail.png","storage/app/public/thumbnails/","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/I3C_Architecture_eLearning_Course_thumbnail.png",{"id":49,"name":50,"slug":51,"description":52,"whats_included":53,"about":54,"instructor_fullname":55,"instructor_email":56,"equivelent_of":14,"subscription_length":30,"price":57,"price_arbor":57,"course_category_id":32,"elearning_courses":58,"you_will_learn":59,"prerequisites":35,"is_active":13,"modified_at":60,"order":61,"modules_count":62,"video":63},1757,"Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4) eLearning Course","modern-dram-ddr5-ddr4-lpddr5-lpddr4-elearning-course","\u003Cp>This course is hardware-centric and also describes initialization and training of DRAM devices and controllers. It is suitable for hardware engineers and software/firmware engineers will also benefit. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers. This course introduces current DRAM technologies, concentrating on DDR4 as a baseline to teach concepts that are common to all DRAMs. The course then continues to cover in detail all new features of DDR5, DDR4, LPDDR5, and LPDDR4.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/ddr5_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/ddr5_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>DRAM eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"DRAM\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","John Swindle","john.swindle@mindshare.com","1595",[],"\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Where JEDEC expects DRAM to appear in a system\u003C/li>\r\n\u003Cli>How a DRAM cell is addressed by the controller\u003C/li>\r\n\u003Cli>Difference between Banks, Bank Groups and Ranks\u003C/li>\r\n\u003Cli>Why the DRAM controller is so complicated\u003C/li>\r\n\u003Cli>Activation, Precharge and Refresh\u003C/li>\r\n\u003Cli>DDR4 pin definitions\u003C/li>\r\n\u003Cli>DDR4 bank state diagram\u003C/li>\r\n\u003Cli>DDR4 timing waveforms\u003C/li>\r\n\u003Cli>Prefetch Width\u003C/li>\r\n\u003Cli>Types of DIMMs\u003C/li>\r\n\u003Cli>Fly-By Routing\u003C/li>\r\n\u003Cli>PC and LP DRAM device architectures and features including DDR5 and LPDDR5\u003C/li>\r\n\u003Cli>DDR5/LPDDR4/LPDDR5 pin definitions\u003C/li>\r\n\u003Cli>DDR5/LPDDR4/LPDDR5 bank state diagrams\u003C/li>\r\n\u003Cli>DDR5/LPDDR4/LPDDR5 timing waveforms\u003C/li>\r\n\u003Cli>DDR5 DIMM PMIC\u003C/li>\r\n\u003Cli>Intro to NVDIMM\u003C/li>\r\n\u003Cli>Newer forms of Refresh\u003C/li>\r\n\u003Cli>POD and LVSTL signaling\u003C/li>\r\n\u003Cli>Clock throttling and dynamic voltage changes\u003C/li>\r\n\u003Cli>On-Die Termination (ODT)\u003C/li>\r\n\u003Cli>JEDEC Initialization and Mode Registers\u003C/li>\r\n\u003Cli>Calibration and training, including\r\n\u003Cul>\r\n\u003Cli>Vref training\u003C/li>\r\n\u003Cli>Read and Write calibration\u003C/li>\r\n\u003Cli>Write Leveling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Sources of errors and JEDEC features for handling errors\u003C/li>\r\n\u003Cli>Test philosophy and JEDEC features to assist with testing\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","2025-02-17 15:43:28",1,111,{"id":64,"local_path":41,"file_name":65,"mime":16,"vimeo_uri":66,"duration":67,"thumbnail_filename":68,"local_thumbnail_path":46,"thumbnail_url":69},37763,"legacy-744751492.mp4","/videos/744751492",104,"Modern_DRAM_(DDR5_/_DDR4_/_LPDDR5_/_LPDDR4)_eLearning_Course_thumbnail.png","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/Modern_DRAM_%28DDR5_/_DDR4_/_LPDDR5_/_LPDDR4%29_eLearning_Course_thumbnail.png",{"id":71,"name":72,"slug":73,"description":74,"whats_included":75,"about":54,"instructor_fullname":55,"instructor_email":56,"equivelent_of":61,"subscription_length":30,"price":31,"price_arbor":31,"course_category_id":32,"elearning_courses":76,"you_will_learn":77,"prerequisites":78,"is_active":13,"modified_at":79,"order":29,"modules_count":80,"video":81},1760,"Fundamentals of DRAM eLearning Course","fundamentals-of-dram","\u003Cp>\u003Cstrong>Note: This course is a subset of the comprehensive course entitled: Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4) eLearning Course\u003C/strong>.\u003C/p>\r\n\u003Cp>If you purchase this fundamentals course and then want to upgrade to the comprehensive course, you will only have to pay the difference for the upgrade.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/fund_dram_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/fund_dram_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>DRAM eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>",[],"\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>Where JEDEC expects DRAM to appear in a system\u003C/li>\r\n\u003Cli>How a DRAM cell is addressed by the controller\u003C/li>\r\n\u003Cli>Difference between Banks, Bank Groups and Ranks\u003C/li>\r\n\u003Cli>Why the DRAM controller is so complicated\u003C/li>\r\n\u003Cli>Activation, Precharge and Refresh\u003C/li>\r\n\u003Cli>DDR4 pin definitions\u003C/li>\r\n\u003Cli>DDR4 bank state diagram\u003C/li>\r\n\u003Cli>DDR4 timing waveforms\u003C/li>\r\n\u003Cli>Prefetch Width\u003C/li>\r\n\u003Cli>Types of DIMMS\u003C/li>\r\n\u003Cli>Fly-By Routing\u003C/li>\r\n\u003Cli>PC and LP DRAM device architectures and features including DDR5 and LPDDR5\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","\u003Cp>None.\u003C/p>","2025-08-11 21:03:00",33,{"id":82,"local_path":41,"file_name":65,"mime":16,"vimeo_uri":66,"duration":83,"thumbnail_filename":84,"local_thumbnail_path":46,"thumbnail_url":85},37766,0,"Fundamentals_of_DRAM_eLearning_Course_thumbnail.png","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/Fundamentals_of_DRAM_eLearning_Course_thumbnail.png",[],[88,96,104],{"id":89,"course_name":90,"classroom_info":15,"virtual_classroom_info":91,"file_url":92,"course_link":93,"link":94,"file_name":95},179,"Modern DRAM (DDRx / LPDDRx)","8 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_Comprehensive_DRAM_DDR5_LPDDR6_Outline.pdf","/live-training-course/dram-ddr5lpddr5-architecture","/elearning-course/modern-dram-ddr5-ddr4-lpddr5-lpddr4-elearning-course","MindShare_Comprehensive_DRAM_DDR5_LPDDR6_Outline.pdf",{"id":97,"course_name":98,"classroom_info":99,"virtual_classroom_info":100,"file_url":101,"course_link":93,"link":102,"file_name":103},182,"Fundamentals of DRAM","1 day","2 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_Fundamentals_DRAM_DDRx_LPDDRx_Outline.pdf","/elearning-course/fundamentals-of-dram","MindShare_Fundamentals_DRAM_DDRx_LPDDRx_Outline.pdf",{"id":105,"course_name":106,"classroom_info":107,"virtual_classroom_info":108,"file_url":109,"course_link":110,"link":111,"file_name":112},181,"MIPI I3C Architecture","3 days","6 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_I3C_Outline.pdf","/live-training-course/mipi-i3c","/elearning-course/i3c-architecture-elearning-course","MindShare_I3C_Outline.pdf",[16],"DRAM Architecture","DDR, DDR5, LPDDR5, LPDDR6 DRAM Architecture","DDR, DDR5, LPDDR5, LPDDR6 DRAM Architecture, DRAM Training",1793031959002]