[{"data":1,"prerenderedAt":124},["ShallowReactive",2],{"GET-live-training-course/slug/serial-ata-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":16,"course_outline":17,"supplied_materials":16,"thumbnail":18,"elearning_courses":19,"ebooks":68,"topics":100,"reviews":123,"meta_title":16,"meta_description":16,"meta_keywords":16},708,"SATA - Serial ATA","serial-ata","\u003Cp>MindShare brings the SATA course to life through its interactive classroom style, demonstrations, and hands-on exercises. This course covers the SATA 3.2 specification from a hardware design perspective and also discusses the software requirements of SATA implementations (Includes SATA Express and M.2). The Advanced Host Controller Interface (AHCI) is also described along with its numerous registers.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp class=\"sectionsubhead\">\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"Serial ATA\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli>PDF of course slides\u003C/li>\r\n\u003Cli>\"\u003Ca href=\"../../ebook/sata-storage-technology\">SATA Storage Technology\u003C/a>\" eBook\u003C/li>\r\n\u003Cli>Optional add-on: \u003Ca href=\"../../elearning-course/sata-32-technology-elearning-course\">SATA 3.2 Technology eLearning course\u003C/a>\u003C/li>\r\n\u003Cli>Optional add-on: \u003Ca href=\"../../elearning-course/advanced-host-controller-interface-ahci-elearning-course\">Advanced Host Controller Interface (AHCI) eLearning course\u003C/a>\u003C/li>\r\n\u003C/ul>","\u003Cul>\r\n\u003Cli>The The sequence of events associated with SATA initialization, including Out Of Band (OOB) signaling\u003C/li>\r\n\u003Cli>Detailed operation of a SATA HBA and drive when executing legacy commands\u003C/li>\r\n\u003Cli>How to verify proper command protocol associated with each of the command categories\u003C/li>\r\n\u003Cli>How to verify proper control protocol associated with writes to the Control register\u003C/li>\r\n\u003Cli>How to validate proper FIS (Frame Information Structure) protocol given trace captures from a SATA protocol analyzer\u003C/li>\r\n\u003Cli>The actions taken by each layer in the SATA interface\u003C/li>\r\n\u003Cli>The details associated with the implementation of Port Multipliers\u003C/li>\r\n\u003Cli>The operation and performance advantages of Native Command Queuing (NCQ)\u003C/li>\r\n\u003Cli>SATA Express implementation and features\u003C/li>\r\n\u003Cli>M.2 sockets and modules for SSD applications\u003C/li>\r\n\u003Cli>Advanced Host Controller Interface (AHCI) fundamentals\u003C/li>\r\n\u003Cli>How to use Arbor to view AHCI registers\u003C/li>\r\n\u003C/ul>","\u003Cp>A solid understanding of one or more storage bus protocols such as ATA or similar architecture is recommended but not required.\u003C/p>",true,10,"3 days",null,"\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part I: SATA Overview\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>Evolution of Parallel ATA\u003C/li>\r\n\u003Cli>Motivation for SATA\u003C/li>\r\n\u003Cli>SATA Overview\u003Cbr>\r\n\u003Cul>\r\n\u003Cli>\u003Cstrong>HANDS-ON ARBOR LAB\u003C/strong>: Scan system and understand Arbor features\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part II: FIS Transmission Protocols\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>FIS Types & Formats\u003C/li>\r\n\u003Cli>Transport & Link Protocol Details\u003C/li>\r\n\u003Cli>FIS Retry (Transport Layer)\u003C/li>\r\n\u003Cli>Data Flow Control\u003C/li>\r\n\u003Cli>Physical Layer Functions\u003C/li>\r\n\u003Cli>Error Detection & Handling\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part III: Command & Control Protocols\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>Device Control Protocols\u003C/li>\r\n\u003Cli>Device Command Protocols\u003C/li>\r\n\u003Cli>Native Command Queuing (NCQ)\u003C/li>\r\n\u003Cli>NCQ Protocols\u003C/li>\r\n\u003Cli>New Commands & Subcommands\u003C/li>\r\n\u003Cli>NCQ Log Addresses\r\n\u003Cul>\r\n\u003Cli>\u003Cstrong>HANDS-ON ARBOR LAB\u003C/strong>: Verify NCQ operation\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part IV: Server Implementations\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>Port Multipliers\u003C/li>\r\n\u003Cli>Port Selectors\u003C/li>\r\n\u003Cli>Enclosure Services\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part V: Physical Layer Details\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>SATA Initialization\u003C/li>\r\n\u003Cli>AFE & Electrical Details\u003C/li>\r\n\u003Cli>Link Power Management\u003C/li>\r\n\u003Cli>Hot Plug\u003C/li>\r\n\u003Cli>Built-In Test (BIST)\u003C/li>\r\n\u003Cli>Cables/Connectors\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part VI SATA Express (SATA-IO) Overview\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>Introduction to SATA Express\u003C/li>\r\n\u003Cli>SATA Express Connectors / Receptacles\u003C/li>\r\n\u003Cli>PCIe Drives/SATA Drives/SATA Legacy Drives\u003C/li>\r\n\u003Cli>Connector Matrix\u003C/li>\r\n\u003Cli>SATA Express Pinouts\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part VII M.2 Sockets & Modules (PCI SIG) Overview\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>Introduction to M.2\u003C/li>\r\n\u003Cli>Socket 2 & Socket 3 for SSDs\u003C/li>\r\n\u003Cli>M.2 Supports SATA/PCIe Speeds\u003C/li>\r\n\u003Cli>Module dimensions\u003C/li>\r\n\u003Cli>M.2 Pinouts\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"text-decoration: underline;\">\u003Cstrong>Part VIII: Advanced Host Controller Interface Overview\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>PCIe Configuration of AHCI\r\n\u003Cul>\r\n\u003Cli>\u003Cstrong>HANDS-ON ARBOR LAB\u003C/strong>: Evaluating the AHCI Capability Registers\u003C/li>\r\n\u003Cli>\u003Cstrong>HANDS-ON ARBOR LAB\u003C/strong>: Evaluating the Port Registers\u003C/li>\r\n\u003Cli>\u003Cstrong>HANDS-ON ARBOR LAB\u003C/strong>: Evaluating the Memory Structures\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_708_thumbnail_1747669010.png",[20,47],{"id":21,"name":22,"slug":23,"description":24,"whats_included":25,"about":26,"instructor_fullname":27,"instructor_email":28,"equivelent_of":29,"subscription_length":30,"price":31,"price_arbor":31,"course_category_id":32,"elearning_courses":33,"you_will_learn":34,"prerequisites":35,"is_active":13,"modified_at":16,"order":36,"modules_count":37,"video":38},1718,"SATA 3.2 Technology eLearning Course","sata-32-technology-elearning-course","\u003Cp>MindShare brings the SATA course to life through its interactive classroom style, demonstrations, and hands-on exercises. This course covers the SATA 3.2 specification from a hardware design perspective and also discusses the software requirements of SATA implementations (Includes SATA Express and M.2). The Advanced Host Controller Interface (AHCI) is also described along with its numerous registers.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/sata3_modules.png\" alt=\"PCIe Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/sata3_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/sata_ebook.jpg\" alt=\"PCIe eBook\" width=\"130\" height=\"145\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>SATA 3.2 eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>SATA eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"SATA\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","Mike Jackson","mike@mindshare.com",3,120,"795",18,[],"\u003Cdiv>\r\n\u003Cul>\r\n\u003Cli>The sequence of events associated with SATA initialization, including Out Of Band (OOB) signaling\u003C/li>\r\n\u003Cli>Details regarding the implementation and operation of the Advanced Host Controller Interface (AHCI)\u003C/li>\r\n\u003Cli>How to verify proper command protocol associated with each of the command categories\u003C/li>\r\n\u003Cli>How to verify proper control protocol associated with writes to the Control register\u003C/li>\r\n\u003Cli>The actions taken by each layer in the SATA interface\u003C/li>\r\n\u003Cli>The details associated with the implementation of Port Multipliers\u003C/li>\r\n\u003Cli>The operation and performance advantages of Native Command Queuing (NCQ)\u003C/li>\r\n\u003Cli>The new features associated with the SATA Express SSDs and M.2 mobile cards\u003C/li>\r\n\u003Cli>How the three SATA Express drives are detected\u003C/li>\r\n\u003Cli>The mating compatibility of the SATA Express plug and receptacles\u003C/li>\r\n\u003Cli>The compatibility associated with the M.2 modules and sockets\u003C/li>\r\n\u003C/ul>\r\n\u003C/div>","null",5,21,{"id":39,"local_path":40,"file_name":41,"mime":16,"vimeo_uri":42,"duration":43,"thumbnail_filename":44,"local_thumbnail_path":45,"thumbnail_url":46},37724,"storage/app/videos/legacy/previews/","legacy-417348271.mp4","/videos/417348271",0,"SATA_3.2_Technology_eLearning_Course_thumbnail.png","storage/app/public/thumbnails/","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/SATA_3.2_Technology_eLearning_Course_thumbnail.png",{"id":48,"name":49,"slug":50,"description":51,"whats_included":52,"about":53,"instructor_fullname":27,"instructor_email":28,"equivelent_of":54,"subscription_length":30,"price":55,"price_arbor":55,"course_category_id":56,"elearning_courses":57,"you_will_learn":58,"prerequisites":59,"is_active":13,"modified_at":16,"order":60,"modules_count":61,"video":62},1748,"PIPE 6.0 - PHY Interface for PCI Express and more","pipe-60-phy-interface-for-pci-express-and-more","\u003Cp>PIPE 6.0 enables the development of PHYs for PCI Express, SATA, USB, DisplayPort, and USB4. Such PIPE compliant PHYs can be delivered as standalone ICs or as macrocell IPs for inclusion in ASICs. The course describes a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. Two independently designed PHY and MAC ASICs/macrocell IPs will connect and work together as long as they meet the design requirements of PIPE 6.0. This course does not describe the internal design of a compliant PHY chip or higher layer protocol architecture. To understand PCIe, SATA or USB architecture, you would need to take one of MindShare’s other comprehensive architecture courses.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>The course covers PIPE interface operational behavior in PCIe, USB and SATA modes. Additionally, you will also learn the signaling protocol associated with the Link Training process, Equalization process and Lane Margining.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pipe2020_modules.png\" alt=\"Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"35%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/pipe2020_slides.png\" alt=\"img\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PCIe PIPE 6.0 eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume/CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cdiv>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"PIPE 6.0\" to Life for You\u003C/strong>\u003C/span>\u003C/div>",1,"395",147,[],"\u003Cul>\r\n\u003Cli>Signals and protocol associated with communication between the MAC layer (of PCIe, SATA, USB 3.1, USB4 and DisplayPort) and PHY layer\u003C/li>\r\n\u003Cli>Register definitions both in the MAC and PHY layers\u003C/li>\r\n\u003Cli>Signaling to support the PHY equalization process\u003C/li>\r\n\u003Cli>PCIe power state support\u003C/li>\r\n\u003Cli>USB and SATA operational modes\u003C/li>\r\n\u003C/ul>","\u003Cp>A basic understanding of PCI Express, SATA, USB 3.1/USB4 and DisplayPort protocols which serves as a\u003Cbr>basis to understanding the packets and signals that traverse the PIPE interface.\u003C/p>",6,14,{"id":63,"local_path":40,"file_name":64,"mime":16,"vimeo_uri":65,"duration":43,"thumbnail_filename":66,"local_thumbnail_path":45,"thumbnail_url":67},37754,"legacy-469816053.mp4","/videos/469816053","PIPE_6.0_-_PHY_Interface_for_PCI_Express_and_more_thumbnail.png","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/PIPE_6.0_-_PHY_Interface_for_PCI_Express_and_more_thumbnail.png",[69],{"id":70,"name":71,"slug":72,"category_id":54,"author":16,"revision":73,"errata_text":74,"errata_link":16,"price":16,"file_path":75,"file_name":76,"cover_url":77,"peek_inside_file":16,"peek_inside_url":16,"overview":78,"has_book":79,"book_out_of_stock":79,"key_topics":80,"about_the_authors":81,"info":82,"authors":83,"publisher":84,"pages":85,"retail_price":86,"ebook_price":87,"book_price":88,"combined_price":88,"tags":89,"price_type":90,"related_items":91,"shipping_details":92,"is_active":13,"meta_title":16,"meta_description":95,"meta_keywords":96,"user_ebook":97},376,"SATA Storage Technology","sata-storage-technology","1.1","Errata as of May, 8, 2017","storage/app/ebooks/legacy/protected/","MindShare_SATA_eBook_v1.1.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/SATA_Storage_Technology_cover-2025-06-30_15%3A19%3A29.jpg","\u003Ci>SATA Storage Technology\u003C/i> provides ATA background information necessary to understand the Serial ATA implementation. This book provides detailed information regarding the serial protocol, commands, and electrical interface.",false,"\u003Cp>The SATA (Serial ATA) interface is intended to expand and eventually replace the parallel ATA interface that has been the standard connection for hard drives and CD-ROM/DVD drives in Personal Computers for nearly twenty years. SATA, a high-speed serial version of ATA, is designed to maintain compatibility with software written for the standard ATA implementation, thus easing the transition to SATA. New advances in SATA provide new capabilities such as Native Command Queuing that improve overall drive performance and greater reliability. In addition, the latest version of SATA (called SATA II) adds new features such as higher transfer rates, Port Selectors, Port Multipliers, and enclosure services, making it easier to implement low cost, high capacity, storage subsystems for server implementations. This book provides essential information for Systems Engineers, System Validation Engineers, Hardware Designers, and Software Developers.\u003Cbr>\u003Cspan style=\"font-style: italic;\">SATA Storage Technology\u003C/span> provides ATA background information necessary to understand the Serial ATA implementation. This book provides detailed information regarding the serial protocol, commands, and electrical interface. A tutorial approach is taken to facilitate thorough understanding, using numerous illustrations, tables and examples. The text is also designed to provide easy to access valuable reference information.\u003Cbr>\u003Cbr>Book Chapters\u003C/p>\r\n\u003Cul>\r\n\u003Cli>The Evolution of Parallel ATA\u003C/li>\r\n\u003Cli>The Motivation for SATA\u003C/li>\r\n\u003Cli>SATA Overview\u003C/li>\r\n\u003Cli>Introduction to FIS Transfers\u003C/li>\r\n\u003Cli>FIS Types and Formats\u003C/li>\r\n\u003Cli>Transport and Link Protocols\u003C/li>\r\n\u003Cli>FIS Retry\u003C/li>\r\n\u003Cli>Data Flow Control\u003C/li>\r\n\u003Cli>Physical Layer Functions\u003C/li>\r\n\u003Cli>Error Detection\u003C/li>\r\n\u003Cli>The Command Protocol\u003C/li>\r\n\u003Cli>The Control Protocol\u003C/li>\r\n\u003Cli>Sata II Features\u003C/li>\r\n\u003Cli>Native Command Queuing\u003C/li>\r\n\u003Cli>Port Multipliers\u003C/li>\r\n\u003Cli>Port Selectors\u003C/li>\r\n\u003Cli>Enclosure Services\u003C/li>\r\n\u003Cli>SATA Initialization\u003C/li>\r\n\u003Cli>Physical Layer\u003C/li>\r\n\u003Cli>Form Factors\u003C/li>\r\n\u003Cli>Hot Plug\u003C/li>\r\n\u003Cli>Link Power Management\u003C/li>\r\n\u003Cli>BIST Features\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cspan style=\"font-weight: bold;\">Don Anderson\u003C/span> has over 30 years of experience in the technical electronics and computer industry. He has authored of fourteen books covering various aspects of computer hardware and system design. Topics include system architectures, parallel bus technologies, serial bus technologies, and processor architectures. Don has trained thousands of engineers in the US and around the world. Before joining MindShare, Don worked for Compaq, Schlumberger, Geosource and Hewlett Packard.\u003Cbr>\u003Cbr>\u003Cspan style=\"font-weight: bold;\">MindShare, Inc.\u003C/span> was founded in 1988 to bring computer architecture-related training to the hardware and software design communities. Since then, we have expanded our course offerings to include SAS™, SATA™, iSCSI, Fibre Channel, PCI Express™, PCI-X™, PCI™ and HyperTransport™ System Architectures as well as Pentium 4 and Opteron Processor Architectures. \u003Cbr>\u003Cbr>MindShare instructors travel the world delivering customized training courses to the very companies that lead the high-tech industry. Our instructors have tremendous computer engineering experience. Our consistent research and training efforts ensure that instructors and authors are always up to date on the latest technological trends.\u003C/p>","\u003Cp>\"This SATA Storage Technology book from MindShare is the ultimate tutorial on the SATA specification and its implementation. Any SATA-based product developer will find the clear and concise explanations of the various features found in this protocol to be invaluable. Particular emphasis is placed on the sections of the spec that enable SATA to be such an important interface for enterprise storage systems.\"\u003Cbr>     - Mark Adams, Product Marketing Manager of the LeCroy Corporation\u003C/p>","Don Anderson","MindShare Press",496,"59.99","30","0",[],"ebook_price",[],{"book_width":93,"book_length":93,"book_height":93,"book_weight":94},0.01,0.003,"MindShare SATA book","sata, serial ata, book, mindshare",{"id":98,"presentation_id":16,"downloaded":79,"signed_file_name":16,"watermark_status":99,"is_new":79,"revision":16},63756,"WATERMARK_NOT_CREATED",[101,109,116],{"id":102,"course_name":103,"classroom_info":15,"virtual_classroom_info":104,"file_url":105,"course_link":106,"link":107,"file_name":108},153,"SATA 3.2","6 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_SATA_3_AHCI_Agenda.pdf","/live-training-course/serial-ata","/elearning-course/sata-32-technology-elearning-course","MindShare_SATA_3_AHCI_Agenda.pdf",{"id":110,"course_name":49,"classroom_info":111,"virtual_classroom_info":112,"file_url":113,"course_link":16,"link":114,"file_name":115},172,"1 day","2 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_PIPE6_Outline.pdf","/elearning-course/pipe-60-phy-interface-for-pci-express-and-more","MindShare_PIPE6_Outline.pdf",{"id":117,"course_name":118,"classroom_info":15,"virtual_classroom_info":104,"file_url":119,"course_link":120,"link":121,"file_name":122},161,"SAS 3.0","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_SAS_3_Agenda.pdf","/live-training-course/sas","/elearning-course/sas-30-storage-technology-elearning-course","MindShare_SAS_3_Agenda.pdf",[16],1793031959697]