[{"data":1,"prerenderedAt":30},["ShallowReactive",2],{"GET-live-training-course/slug/ucie-universal-chiplet-interconnect-express-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":16,"course_outline":17,"supplied_materials":16,"thumbnail":18,"elearning_courses":19,"ebooks":20,"topics":21,"reviews":29,"meta_title":16,"meta_description":16,"meta_keywords":16},740,"UCIe - Universal Chiplet Interconnect Express","ucie-universal-chiplet-interconnect-express","\u003Cp>Universal Chiplet Interconnect Express (UCIe) is an open industry standard, multi-protocol, high-bandwidth (up to 32GT/s per lane), die-to-die (chiplet), interconnect that standardizes inter-die communication on-package. The UCIe 1.1 specification enables users to mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) build. The UCIe spec describes a standardized port and interconnect with physical layer, protocol stack and software model that enables inter-chiplet communication. UCIe supports multiple protocols such as PCIe, CXL, and a raw mode that can be used to map any protocol of choice (assuming both ends support it) on top of a common Physical and Link layer. The spec describes elements needed for SoC design such as the application layer, form-factors relevant to the package including bump location, power delivery and thermal solution.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>The initial protocols being mapped to UCIe are PCIe and CXL and are done using a Flit packet format for communication. Both PCIe and CXL protocol mappings will enable more on-package integration by replacing the PCIe SERDES PHY, the PCIe/CXL Logical Physical layer and the Link Level Retry (LLR) state-machines with a UCIe Adapter and PHY in order to improve the power and performance characteristics. UCIe also supports a protocol-agnostic raw mode to enable other protocols to be mapped.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>MindShare’s comprehensive UCIe Architecture course provides a solid foundation to understanding die-to-die architecture and use of UCIe retimers to extend connectivity beyond the package. The course describes port architecture details including protocol layer, die-to-die adapter layer, logical physical layer and electrical physical layer. We describe single and multi-module configurations. In addition, the course describes the sideband architecture details. Sideband interface is used for back-channel Link training, access to registers, Link management packets and parameter exchanges with remote Link partner. UCIe register architecture and the mechanism by which UCIe-aware SW discovers UCIe capability is described. An optional section describes a Raw Die-to-Die Interface (RDI) and Flit-aware Die-to-Die Interface (FDI) between the die-to-die adapter layer and physical layer.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"UCIe\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli>PDF of course slides\u003C/li>\r\n\u003Cli>Optional add-on: UCIe 1.0 eLearning course (when available)\u003C/li>\r\n\u003C/ul>","\u003Cul>\r\n\u003Cli>UCIe system architecture used for die-to-die communication including use of UCIe retimers\u003C/li>\r\n\u003Cli>UCIe for tunneling PCIe, CXL and other protocols in raw mode\u003C/li>\r\n\u003Cli>UCIe port design constituting Protocol, Die-to-Die Adapter, Logical and Electrical Physical Layers\u003C/li>\r\n\u003Cli>Sideband interface usage and protocol\u003C/li>\r\n\u003Cli>Software view of UCIe when paired with PCIe or CXL protocol layers\u003C/li>\r\n\u003Cli>UCIe Interface (RDI and FDI) architecture between the Die-to-Die Adapter layer and Physical layer. (This topic is optionally covered.)\u003C/li>\r\n\u003C/ul>","\u003Cp>A good working knowledge of PCI Express (PCIe) and Compute Express Link (CXL) is a must. Computer architecture fundamentals. Some knowledge of Intel, AMD or Arm processor architectures.\u003C/p>",true,11,"2 days",null,"\u003Cul>\r\n\u003Cli>UCIe Features and Architecture Overview\r\n\u003Cul>\r\n\u003Cli>Package and platform architecture based on UCIe\u003C/li>\r\n\u003Cli>Overview of UCIe port architecture\r\n\u003Cul>\r\n\u003Cli>Protocol layer\u003C/li>\r\n\u003Cli>Die-to-Die Adapter layer\u003C/li>\r\n\u003Cli>Logical and Electrical Physical layer\u003C/li>\r\n\u003Cli>Sideband interface\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>UCIe Retimers\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>UCIe Protocol Layer : Protocols and Flit Formats\r\n\u003Cul>\r\n\u003Cli>Protocols or Modes of operation\r\n\u003Cul>\r\n\u003Cli>68B-Flit Mode\"\u003C/li>\r\n\u003Cli>CXL 256B Flit Mode\u003C/li>\r\n\u003Cli>PCIe Flit Mode\u003C/li>\r\n\u003Cli>Streaming Mode\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Flit Formats\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>UCIe Die-to-Die Adapter Layer\r\n\u003Cul>\r\n\u003Cli>Link/Adapter initialization\u003C/li>\r\n\u003Cli>Power management link states\u003C/li>\r\n\u003Cli>Retry rules\u003C/li>\r\n\u003Cli>Parity-based runtime Link testing\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>UCIe Logical Physical Layer\r\n\u003Cul>\r\n\u003Cli>Data and sideband transmission flows\u003C/li>\r\n\u003Cli>Lane reversal\u003C/li>\r\n\u003Cli>Interconnect redundancy map\u003C/li>\r\n\u003Cli>Data to clock training and test modes\u003C/li>\r\n\u003Cli>Link Initialization and Training\u003C/li>\r\n\u003Cli>Runtime recalibration\u003C/li>\r\n\u003Cli>Multi-module Link initialization\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>UCIe Electrical Physical Layer\r\n\u003Cul>\r\n\u003Cli>Interoperability of data rates\u003C/li>\r\n\u003Cli>Tx spec\u003C/li>\r\n\u003Cli>Rx spec\u003C/li>\r\n\u003Cli>Clocking\u003C/li>\r\n\u003Cli>Supply noise and clock skew\u003C/li>\r\n\u003Cli>Ball-out and channel spec\u003C/li>\r\n\u003Cli>Tightly coupled mode\u003C/li>\r\n\u003Cli>Interconnect reducancy mapping\u003C/li>\r\n\u003Cli>BER requirements\u003C/li>\r\n\u003Cli>Valid and clock gating\u003C/li>\r\n\u003Cli>Electrical Idle\u003C/li>\r\n\u003Cli>Sideband signaling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Sideband Interface\r\n\u003Cul>\r\n\u003Cli>Packet types and formats\u003C/li>\r\n\u003Cli>Flow control and data integrity\u003C/li>\r\n\u003Cli>Operation on RDI and FDI\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>UCIe DVSEC and Register Blocks\r\n\u003Cul>\r\n\u003Cli>Software view of UCIe\u003C/li>\r\n\u003Cli>UCIe registers\u003C/li>\r\n\u003Cli>UCIe Interrupt architecture\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>UCIe Interfaces between Protocol Layer, Die-to-Die Adapter and Physical Layer\r\n\u003Cul>\r\n\u003Cli>Raw Die-to-Die Interface (RDI)\u003C/li>\r\n\u003Cli>Flit-Aware Die-to-Die Interface (FDI)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_740_thumbnail_1735844472.png",[],[],[22],{"id":23,"course_name":24,"classroom_info":15,"virtual_classroom_info":25,"file_url":26,"course_link":27,"link":16,"file_name":28},199,"UCIe","4 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_UCIe_Architecture_Outline.pdf","/live-training-course/ucie-universal-chiplet-interconnect-express","MindShare_UCIe_Architecture_Outline.pdf",[16],1793031958767]