[{"data":1,"prerenderedAt":118},["ShallowReactive",2],{"GET-live-training-course/slug/x86-64bit-architecture-{}-{}":3},{"data":4},{"id":5,"name":6,"slug":7,"description":8,"about":9,"training_materials":10,"you_will_learn":11,"prerequisites":12,"is_active":13,"category_id":14,"duration":15,"modified_at":16,"course_outline":17,"supplied_materials":16,"thumbnail":18,"elearning_courses":19,"ebooks":71,"topics":102,"reviews":117,"meta_title":16,"meta_description":16,"meta_keywords":16},698,"x86 64-bit Architecture","x86-64bit-architecture","\u003Cp>This course teaches the x86 architecture (both 32-bit and 64-bit) through a mix of lectures and hands-on programming labs. All topics are explained in lecture format first and then the students are given programming labs in Assembly Language to reinforce the concepts and to get hands-on experience working with x86 processors at a very low level.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cspan style=\"color: rgb(186, 55, 42);\">\u003Cstrong>All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.\u003C/strong>\u003C/span>\u003C/p>","\u003Cp class=\"sectionsubhead\">\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"x86 64-bit Architecture\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli>PDF of course slides\u003C/li>\r\n\u003Cli>\"\u003Ca href=\"../../ebook/x86-instruction-set-architecture\">x86 Instruction Set Architecture\u003C/a>\" eBook\u003C/li>\r\n\u003C/ul>","\u003Cul>\r\n\u003Cli>x86 architecture basics like an overview of the instruction set, register set and operating modes\u003C/li>\r\n\u003Cli>The behavior of segmentation, how it was originally intended to be used and how it is actually used by operating systems today (both 32-bit and 64-bit OSs)\u003C/li>\r\n\u003Cli>How to setup system calls using multiple methods (and what are benefits / side-effects of each)\u003C/li>\r\n\u003Cli>How to setup interrupt service routines for both software and hardware interrupts as well as exceptions\u003C/li>\r\n\u003Cli>How to implement paging in both the 32-bit environments as well as the 64-bit environments including using various page sizes\u003C/li>\r\n\u003Cli>What the concepts of virtualization are and the behavior of the x86 hardware extensions for virtualization (including benefits and side-effects)\u003C/li>\r\n\u003C/ul>","\u003Cp>General familiarity with computer architecture is recommended.\u003C/p>",true,8,"5 days",null,"\u003Cul>\r\n                \u003Cli>x86 Instruction Set Background\u003C/li>\r\n                \u003Cli>Intro to the Instruction Set\r\n                \u003Cul>\r\n                    \u003Cli>General Purpose Instructions\u003C/li>\r\n                    \u003Cli>Floating Point and SIMD Instructions\r\n                    \u003Cul>\r\n                        \u003Cli>x87, MMX, SSE, AVX, AVX-2, AVX-512\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Program Flow-related Instructions\u003C/li>\r\n                    \u003Cli>Hardware-Related Instructions\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Intro to the Register Set and Address Spaces\r\n                \u003Cul>\r\n                    \u003Cli>General Purpose registers (GPRs)\u003C/li>\r\n                    \u003Cli>x87 / MMX registers\u003C/li>\r\n                    \u003Cli>XMM / YMM /ZMM registers\u003C/li>\r\n                    \u003Cli>Segmentation registers\u003C/li>\r\n                    \u003Cli>Control registers\u003C/li>\r\n                    \u003Cli>Debug registers\u003C/li>\r\n                    \u003Cli>Model-Specific registers (MSRs)\u003C/li>\r\n                    \u003Cli>Memory, IO, and Configuration Spaces\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Operating Modes\r\n                \u003Cul>\r\n                    \u003Cli>Real Mode\u003C/li>\r\n                    \u003Cli>Protected Mode\u003C/li>\r\n                    \u003Cli>Virtual-8086 Mode\u003C/li>\r\n                    \u003Cli>System Management Mode\u003C/li>\r\n                    \u003Cli>Long (IA32e) Mode\r\n                    \u003Cul>\r\n                        \u003Cli>64-bit Mode\r\n                        \u003Cul>\r\n                            \u003Cli>REX prefixes\u003C/li>\r\n                        \u003C/ul>\r\n                        \u003C/li>\r\n                        \u003Cli>Compatibility Mode\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Real Mode Operation\u003C/li>\r\n                \u003Cli>Introduction to Multitasking\u003C/li>\r\n                \u003Cli>Segmentation (Protected Mode)\r\n                \u003Cul>\r\n                    \u003Cli>Privilege Levels (Rings)\u003C/li>\r\n                    \u003Cli>Code and Data Segment Descriptors\u003C/li>\r\n                    \u003Cli>Segment Registers (CS, SS, DS, ES, FS, GS)\u003C/li>\r\n                    \u003Cli>Global Descriptor Table (GDT)\u003C/li>\r\n                    \u003Cli>Local Descriptor Table (LDT)\u003C/li>\r\n                    \u003Cli>Flat memory model vs protected memory model\u003C/li>\r\n                    \u003Cli>\u003Cspan style=\"color: rgb(153, 51, 0);\">HANDS-ON LAB:\u003C/span> covering Protected Mode Segmentation\u003C/li>\r\n                    \u003Cli>Segmentation in Long Mode\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Control Transfers\r\n                \u003Cul>\r\n                    \u003Cli>Far Jumps and Calls\u003C/li>\r\n                    \u003Cli>Call Gates\u003C/li>\r\n                    \u003Cli>Optimized System Calls\r\n                    \u003Cul>\r\n                        \u003Cli>SYSCALL / SYSRET\u003C/li>\r\n                        \u003Cli>SYSENTER / SYSEXIT\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Automatic Stack Switching\u003C/li>\r\n                    \u003Cli>\u003Cspan style=\"color: rgb(153, 51, 0);\">HANDS-ON LAB:\u003C/span> covering system calls\u003C/li>\r\n                    \u003Cli>Control Transfers in Long Mode\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Task Management\r\n                \u003Cul>\r\n                    \u003Cli>Software vs. Hardware task switching\u003C/li>\r\n                    \u003Cli>Task State Segments (TSS)\u003C/li>\r\n                    \u003Cli>Task Gates\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Interrupts and Exceptions\r\n                \u003Cul>\r\n                    \u003Cli>Hardware vs. Software interrupts\u003C/li>\r\n                    \u003Cli>Vectors\u003C/li>\r\n                    \u003Cli>Interrupt priorities\u003C/li>\r\n                    \u003Cli>Exceptions and their classifications (faults, traps and aborts)\u003C/li>\r\n                    \u003Cli>Interrupt Descriptor Table (IDT)\u003C/li>\r\n                    \u003Cli>Interrupt Gates vs Trap Gates\u003C/li>\r\n                    \u003Cli>Stack behavior on an interrupt / exception\r\n                    \u003Cul>\r\n                        \u003Cli>Error codes\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>\u003Cspan style=\"color: rgb(153, 51, 0);\">HANDS-ON LAB:\u003C/span> covering interrupt handling\u003C/li>\r\n                    \u003Cli>Interrupt handling in Long Mode\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Paging\r\n                \u003Cul>\r\n                    \u003Cli>Purpose of Paging\u003C/li>\r\n                    \u003Cli>Paging Basics\r\n                    \u003Cul>\r\n                        \u003Cli>Physical vs. Virtual (Linear) Address Space\u003C/li>\r\n                        \u003Cli>Swap space (secondary storage)\u003C/li>\r\n                        \u003Cli>x86 paging structures\r\n                        \u003Cul>\r\n                            \u003Cli>Page Directory Entries (PDEs)\u003C/li>\r\n                            \u003Cli>Page Table Entries (PTEs)\u003C/li>\r\n                        \u003C/ul>\r\n                        \u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>TLBs (Translation Lookaside Buffers)\r\n                    \u003Cul>\r\n                        \u003Cli>Managing TLBs (INVLPG, PCID, VPID topics etc.)\u003C/li>\r\n                        \u003Cli>Global pages\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>x86 Paging Modes (features)\r\n                    \u003Cul>\r\n                        \u003Cli>Page Size Extensions (PSE)\u003C/li>\r\n                        \u003Cli>Physical Address Extensions (PAE)\r\n                        \u003Cul>\r\n                            \u003Cli>3-level lookup: Page Directory Pointer Entries (PDPE)\u003C/li>\r\n                        \u003C/ul>\r\n                        \u003C/li>\r\n                        \u003Cli>IA32e (Long) Mode Paging\r\n                        \u003Cul>\r\n                            \u003Cli>4-level lookup: Page Map Level 4 Entries (PML4E)\u003C/li>\r\n                        \u003C/ul>\r\n                        \u003C/li>\r\n                        \u003Cli>Execute Disable functionality\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>\u003Cspan style=\"color: rgb(153, 51, 0);\">HANDS-ON LAB:\u003C/span> covering paging\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Memory Types\r\n                \u003Cul>\r\n                    \u003Cli>Intro to Caches\u003C/li>\r\n                    \u003Cli>Memory Types\r\n                    \u003Cul>\r\n                        \u003Cli>UC – Uncacheable (and UC-)\u003C/li>\r\n                        \u003Cli>WC – Write Combining\u003C/li>\r\n                        \u003Cli>WP – Write Protect\u003C/li>\r\n                        \u003Cli>WT – Write Through\u003C/li>\r\n                        \u003Cli>WB – Write Back\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Assignment Mechanisms\r\n                    \u003Cul>\r\n                        \u003Cli>Memory Type and Range Registers (MTRRs)\u003C/li>\r\n                        \u003Cli>Page Attribute Table Register (PAT)\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Intro to Virtualization Technology (Intel-VT)\r\n                \u003Cul>\r\n                    \u003Cli>What is virtualization\u003C/li>\r\n                    \u003Cli>Hardware extensions: Intel-VTx\r\n                    \u003Cul>\r\n                        \u003Cli>VMX Root Mode (Host Mode) vs VMX non-Root Mode (Guest Mode)\u003C/li>\r\n                        \u003Cli>Virtual Machine Control Structure (VMCS)\u003C/li>\r\n                        \u003Cli>Intel-VT instructions (VMLAUNCH, VMRESUME, etc.) and #VMEXIT\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                    \u003Cli>Memory Management with Virtualization\r\n                    \u003Cul>\r\n                        \u003Cli>Shadow Page Tables\u003C/li>\r\n                        \u003Cli>Extended (Nested) Page Tables\u003C/li>\r\n                        \u003Cli>TLB Management with Virtualization\u003C/li>\r\n                    \u003C/ul>\r\n                    \u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Data Protection Extensions\u003Cbr>\r\n                \u003Cul>\r\n                    \u003Cli>Intel SGX (Software Guard eXtensions)\u003C/li>\r\n                    \u003Cli>Intel MPX (Memory Protection eXtensions)\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>Performance Monitoring\r\n                \u003Cul>\r\n                    \u003Cli>Precision Event Based Sampling (PEBS)\u003C/li>\r\n                \u003C/ul>\r\n                \u003C/li>\r\n                \u003Cli>System Management Mode\u003C/li>\r\n            \u003C/ul>","https://mindshare-prod.s3.amazonaws.com/public/live_training_courses/thumbnails/live_training_course_698_thumbnail_1748360589.png",[20,48],{"id":21,"name":22,"slug":23,"description":24,"whats_included":25,"about":26,"instructor_fullname":27,"instructor_email":28,"equivelent_of":29,"subscription_length":30,"price":31,"price_arbor":31,"course_category_id":32,"elearning_courses":33,"you_will_learn":34,"prerequisites":35,"is_active":13,"modified_at":36,"order":37,"modules_count":38,"video":39},1735,"Intel x86 Processor and Platform Architecture eLearning Course","intel-x86-processor-and-platform-architecture-elearning-course","\u003Cp>Each CPU and chipset generation brings new capabilities while maintaining backward compatibility with earlier platforms. New 9th and 10th generation CPU architectures offer significant improvements in instruction throughput, power conservation, integrated graphics, security, system-on-a-chip (SOC) packaging options, etc. This 5-day course introduces the x86 Instruction Set Architecture (ISA) and describes the hardware features of the latest Intel Core and Xeon CPUs supporting it. In addition, the course presents an overview of memory, platform controller hub (PCH) logic, and IO interfaces that may be employed when implementing common system types.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>A full understanding of an Intel x86 hardware platform includes knowledge of CPU/PCH capabilities, BIOS/OS setup of programmable platform features, as well as the dynamic status of the system with regards to thermal and error events, etc. MindShare Arbor demonstrations integrated into this course present a decoded view of register setup, system and device status, as well as a coherent summary of platform information reported when the CPUID instruction is executed. Students may use Arbor software for real-time scans of local systems, read/modify specific registers, and even save Arbor scan results for later sharing and off-line review.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>This course is updated as frequently as possible in an attempt to provide a “snapshot” of Intel Core and Xeon x86 platform components and system implementations. Content is based on publicly available documents.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86proc_modules.png\" alt=\"PCIe Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86proc_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86_cover_ds.png\" alt=\"PCIe eBook\" width=\"125\" height=\"155\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>Course eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>USB 3.0 eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"Intel Processors and Platforms\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","Jay Trodden","elearning@mindshare.com",5,120,"995",148,[],"\u003Cul>\r\n\u003Cli>Intel x86 CPU and Chipset Evolution\u003C/li>\r\n\u003Cli>Current Core and Xeon CPUs: Ice Lake, Cascade Lake, plus “Refresh” Variants\u003C/li>\r\n\u003Cli>x86 Instruction Set Architecture (ISA) and CPU Operating Modes\u003C/li>\r\n\u003Cli>Core and Xeon CPU Microarchitecture Differences\u003C/li>\r\n\u003Cli>Caches\u003C/li>\r\n\u003Cli>Platform Addressing\u003C/li>\r\n\u003Cli>Main Memory DRAM\u003C/li>\r\n\u003Cli>Ultra Path Interconnect (UPI)\u003C/li>\r\n\u003Cli>CPU Integrated Graphics\u003C/li>\r\n\u003Cli>CPU Integrated IO (IIO)\u003C/li>\r\n\u003Cli>Interrupt Handling\u003C/li>\r\n\u003Cli>Hardware Virtualization Support\u003C/li>\r\n\u003Cli>Platform Controller Hub (PCH) Features\u003C/li>\r\n\u003Cli>Power and Thermal Management\u003C/li>\r\n\u003Cli>CPU Performance Monitoring\u003C/li>\r\n\u003C/ul>","\u003Cp>None.\u003C/p>","2025-08-05 14:37:08",1,57,{"id":40,"local_path":41,"file_name":42,"mime":16,"vimeo_uri":43,"duration":44,"thumbnail_filename":45,"local_thumbnail_path":46,"thumbnail_url":47},37741,"storage/app/videos/legacy/previews/","legacy-417348462.mp4","/videos/417348462",0,"Intel_x86_Processor_and_Platform_Architecture_eLearning_Course_thumbnail.png","storage/app/public/thumbnails/","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/Intel_x86_Processor_and_Platform_Architecture_eLearning_Course_thumbnail.png",{"id":49,"name":50,"slug":51,"description":52,"whats_included":53,"about":54,"instructor_fullname":55,"instructor_email":56,"equivelent_of":57,"subscription_length":30,"price":58,"price_arbor":16,"course_category_id":32,"elearning_courses":59,"you_will_learn":11,"prerequisites":60,"is_active":13,"modified_at":61,"order":44,"modules_count":62,"video":63},1752,"x86 Architecture eLearning Course","x86-architecture-elearning-course","\u003Cp>\u003Cspan style=\"color: rgb(224, 62, 45);\">\u003Cstrong>Note: this course is a subset of our Intel Processor and Platform eLearning Course.\u003C/strong>\u003C/span>\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>This course will be useful for anyone dealing with designing, verifying, validating, debugging, or developing for x86-based platforms. The x86 instruction set architecture has evolved over a period of almost 40 years. This course describes numerous aspects of the current architecture but also explains how we got to the current architecture based on the history and decisions made. It doesn't matter whether you're a hardware engineer or a software developer, this course has an enormous amount of relevant info for you.\u003C/p>","\u003Ctable border=\"0\" cellspacing=\"0\">\r\n\u003Ctbody>\r\n\u003Ctr valign=\"bottom\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86_modules.png\" alt=\"PCIe Modules\" width=\"190\" height=\"135\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86_slides.png\" alt=\"PDF Slides Thumbnail\" width=\"175\" height=\"120\">\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\" width=\"25%\">\u003Cimg style=\"max-height: 150px;\" src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/x86_cover_ds.png\" alt=\"PCIe eBook\" width=\"125\" height=\"155\">\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cimg src=\"https://mindshare-prod.s3.amazonaws.com/public/uploaded/course_certificate160px.png\" alt=\"Course completion certificate\" width=\"213\" height=\"160\">\u003C/td>\r\n\u003C/tr>\r\n\u003Ctr valign=\"top\">\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>Course eLearning modules\u003C/strong>\u003Cbr>(unlimited access for 120 days)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>PDF of Course Slides\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd style=\"border-right: 1px solid rgb(233, 233, 233);\" align=\"center\">\u003Cstrong>x86 Architecture eBook\u003C/strong>\u003Cbr>(yours to keep, does not expire)\u003C/td>\r\n\u003Ctd align=\"center\">\u003Cstrong>Course Completion Certificate\u003C/strong>\u003Cbr>(boost your resume / CV)\u003C/td>\r\n\u003C/tr>\r\n\u003C/tbody>\r\n\u003C/table>","\u003Cp>\u003Cspan style=\"font-size: 18pt;\">\u003Cstrong>Let MindShare Bring \"x86\" to Life for You\u003C/strong>\u003C/span>\u003C/p>","Joe Winkles","joe@mindshare.com",2,"595",[],"\u003Cp>None\u003C/p>","2025-08-05 14:42:57",26,{"id":64,"local_path":65,"file_name":66,"mime":67,"vimeo_uri":68,"duration":44,"thumbnail_filename":69,"local_thumbnail_path":46,"thumbnail_url":70},37758,"public/elearning_courses/teasers/","x86_Architecture_eLearning_Course-2025-07-31_16:02:35.mp4","video/mp4","/videos/1106179335","x86_Architecture_eLearning_Course_thumbnail.png","https://mindshare-prod.s3.amazonaws.com/public/elearning_courses/thumbnails/x86_Architecture_eLearning_Course_thumbnail.png",[72],{"id":73,"name":74,"slug":75,"category_id":37,"author":16,"revision":76,"errata_text":16,"errata_link":16,"price":16,"file_path":77,"file_name":78,"cover_url":79,"peek_inside_file":16,"peek_inside_url":16,"overview":80,"has_book":81,"book_out_of_stock":81,"key_topics":82,"about_the_authors":83,"info":84,"authors":85,"publisher":86,"pages":87,"retail_price":88,"ebook_price":89,"book_price":90,"combined_price":90,"tags":91,"price_type":92,"related_items":93,"shipping_details":94,"is_active":13,"meta_title":16,"meta_description":97,"meta_keywords":98,"user_ebook":99},380,"x86 Instruction Set Architecture","x86-instruction-set-architecture","1.0","storage/app/ebooks/legacy/protected/","MindShare_x86_ISA_eBook_v1.0.pdf","https://mindshare-prod.s3.amazonaws.com/public/ebook_covers/x86_Instruction_Set_Architecture_cover-2025-06-30_15%3A22%3A18.png","\u003Cp>Wikipedia Definition: The Instruction Set Architecture, or ISA, is defined as that part of the processor architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external IO.\u003Cbr>\u003Cbr>Except for some small deviations and differences in terminology, all Intel and AMD x86 processors share a common ISA. This book focuses on those shared attributes (it does not cover those areas where the two companies have chosen widely divergent solutions, which, by definition, fall outside of the ISA specification).\u003Cbr>\u003Cbr>If you’re looking for a comprehensive book designed to bootstrap you up quickly on virtually all aspects of the x86 32/64-bit Instruction Set Architecture (ISA), we respectfully ask you to consider this book. Tom Shanley, President of MindShare, Inc., applied his 40 years of hardware and software experience with Intel processors (from the 4004 and 8008 through the Nehalem-based processors of today) to this ambitious undertaking. The material organization is derived from those used to train thousands of software and hardware designers at virtually all of the world’s leading high-tech companies.\u003C/p>",false,"\u003Cul>\r\n\u003Cli>Basic Terms and Concepts\u003C/li>\r\n\u003Cli>Mode/SubMode Introduction\u003C/li>\r\n\u003Cli>A (very) Brief History\u003C/li>\r\n\u003Cli>State After Reset\u003C/li>\r\n\u003Cli>Intro to the IA-32 Ecosystem\u003C/li>\r\n\u003Cli>Instruction Set Expansion\u003C/li>\r\n\u003Cli>32-bit Machine Language Instruction Format\u003C/li>\r\n\u003Cli>Real Mode (8086 Emulation)\u003C/li>\r\n\u003Cli>Legacy x87 FP Support\u003C/li>\r\n\u003Cli>Introduction to Multitasking\u003C/li>\r\n\u003Cli>Multitasking-Related Issues\u003C/li>\r\n\u003Cli>Summary of the Protection Mechanisms\u003C/li>\r\n\u003Cli>Protected Mode Memory Addressing\u003C/li>\r\n\u003Cli>Code, Calls and Privilege Checks\u003C/li>\r\n\u003Cli>Data and Stack Segments\u003C/li>\r\n\u003Cli>IA-32 Address Translation Mechanisms\u003C/li>\r\n\u003Cli>Memory Type Configuration\u003C/li>\r\n\u003Cli>Task Switching\u003C/li>\r\n\u003Cli>Protected Mode Interrupts and Exceptions\u003C/li>\r\n\u003Cli>Virtual 8086 Mode\u003C/li>\r\n\u003Cli>The MMX Facilities\u003C/li>\r\n\u003Cli>The SSE Facilities\u003C/li>\r\n\u003Cli>IA-32e OS Environment\u003C/li>\r\n\u003Cli>IA-32e Address Translation\u003C/li>\r\n\u003Cli>Compatibility Mode\u003C/li>\r\n\u003Cli>64-bit Register Overview\u003C/li>\r\n\u003Cli>64-bit Operands and Addressing\u003C/li>\r\n\u003Cli>64-bit Machine Language Instruction Format\u003C/li>\r\n\u003Cli>64-bit Odds and Ends\u003C/li>\r\n\u003Cli>Transitioning to Protected Mode\u003C/li>\r\n\u003Cli>Transitioning to IA-32e Mode\u003C/li>\r\n\u003Cli>Introduction to Virtualization Technology\u003C/li>\r\n\u003Cli>System Management Mode (SMM)\u003C/li>\r\n\u003Cli>Machine Check Architecture (MCA)\u003C/li>\r\n\u003Cli>The Local and IO APICs\u003C/li>\r\n\u003C/ul>","\u003Cp>\u003Cstrong>Tom Shanley\u003C/strong>, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.\u003C/p>","\u003Cp>Processor design-specific subjects such as Power Management and design-specific MSRs are not covered in this book. Rather, they are covered in MindShare's Processor family-specific microarchitecture classes.\u003C/p>\r\n\u003Cp>MindShare's System Architecture Series is a crisply written and comprehensive set of guides to the most important computer hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.\u003C/p>","Tom Shanley","MindShare Press",1567,"99.99","40","0",[],"ebook_price",[],{"book_width":95,"book_length":95,"book_height":95,"book_weight":96},0.01,0.008,"MindShare x86 Instruction Set Architecture","x86, intel architecture, amd64, ia-32, intel 64, book, ebook, e-book",{"id":100,"presentation_id":16,"downloaded":81,"signed_file_name":16,"watermark_status":101,"is_new":81,"revision":16},93253,"WATERMARK_NOT_CREATED",[103,111],{"id":104,"course_name":105,"classroom_info":15,"virtual_classroom_info":106,"file_url":107,"course_link":108,"link":109,"file_name":110},160,"Intel x86 Processor and Platform Architecture","10 half-days","https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_Intel_ProcPlat_Agenda.pdf","/live-training-course/intel-processor-and-platform-architecture","/elearning-course/intel-x86-processor-and-platform-architecture-elearning-course","MindShare_Intel_ProcPlat_Agenda.pdf",{"id":112,"course_name":6,"classroom_info":15,"virtual_classroom_info":106,"file_url":113,"course_link":114,"link":115,"file_name":116},176,"https://mindshare-prod.s3.amazonaws.com/public/live_training_course_topics_pdfs/MindShare_x86_Architecture_Outline.pdf","/live-training-course/x86-64bit-architecture","/elearning-course/x86-architecture-elearning-course","MindShare_x86_Architecture_Outline.pdf",[16],1793031959943]