[{"data":1,"prerenderedAt":114},["ShallowReactive",2],{"GET-public-class/slug/pcie67-update-public-class-031627-{}-{}":3,"GET-public-class/visible-future-{}-{}":27},{"id":4,"name":5,"slug":6,"location":7,"start_date_secondary":8,"start_date":9,"end_date_secondary":10,"end_date":11,"format":12,"price":13,"image":14,"details":15,"duration":16,"instructor":17,"prerequisites":18,"outline":19,"visible":20,"meta_title":21,"meta_description":22,"meta_keywords":23,"time":24,"training_materials":25,"button_mode":26},9,"PCI Express (PCIe) 6.x/7.0 Update - 8-Half-Day Course","pcie67-update-public-class-031627","Virtual Classroom","03/22/27","03/16/27","03/25/27","03/19/27","Online","2995.00","https://mindshare-prod.s3.amazonaws.com/public/public-classes/images/CLrWjUz59ujW_PCIe67%20Update.png","\u003Cp class=\"p1\">MindShare's PCI Express 6.x/7.0 Update course starts with a discussion of what’s new in the 6.x and 7.0 specs and why the introduction of PAM4 signaling caused the need for Flits and forward error correction.\u003C/p>\r\n\u003Cp class=\"p1\"> \u003C/p>\r\n\u003Cp class=\"p1\">This MindShare course requires prior knowledge of PCIe 5.0. Only the new features of 6.x and 7.0 are covered with a light review of 5.0 features/behaviors that have changed moving into 6.x and 7.0 with Flit Mode.\u003C/p>","8 half-days","Joe Winkles","\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">A good understanding of PCI Epress 5.0 Architecture.\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli class=\"p1\">Overview of PCIe 6.x/7.0 features\u003C/li>\r\n\u003Cli class=\"p1\">Refresher of PCIe 5.0 topics\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Bus enumeration\u003C/li>\r\n\u003Cli class=\"p1\">TLP and DLLP fields\u003C/li>\r\n\u003Cli class=\"p1\">Flow Control\u003C/li>\r\n\u003Cli class=\"p1\">AckNak error recovery mechanism\u003C/li>\r\n\u003Cli class=\"p1\">Ordered Sets\u003C/li>\r\n\u003Cli class=\"p1\">Equalization mechanism\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">64GT/s and 128GT/s using PAM4 and 1b/1b Encoding at the Physical Layer (PCIe6)\r\n\u003Cul>\r\n\u003Cli class=\"p1\">PAM4\u003C/li>\r\n\u003Cli class=\"p1\">Precoding, Gray Coding and Forward Error Correction (FEC)\u003C/li>\r\n\u003Cli class=\"p1\">LTSSM Updates (TS0s, Tx EQ changes, entering Flit Mode, etc.)\u003C/li>\r\n\u003Cli class=\"p1\">Support of upto 4 Retimers per link\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p2\">Flit Mode\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Flit Format\u003C/li>\r\n\u003Cli class=\"p1\">Error Correction and Flit Retry (Standard vs Selective)\u003C/li>\r\n\u003Cli class=\"p1\">DLP Bytes in Flit and Flit Types\u003C/li>\r\n\u003Cli class=\"p1\">Flow Control (Dedicated vs Shared)\u003C/li>\r\n\u003Cli class=\"p1\">TLP Structure (Header Base, OHC, TLP Trailer, etc.)\u003C/li>\r\n\u003Cli class=\"p1\">Segments\u003C/li>\r\n\u003Cli class=\"p1\">L0p\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Unordered IO (UIO)\u003C/li>\r\n\u003Cli>Overview of PCIe Management Interface (PCIe-MI)\u003C/li>\r\n\u003Cli>Enhanced SFI (eSFI)\u003C/li>\r\n\u003Cli>Shadow Functions vs Phantom Functions\u003C/li>\r\n\u003Cli>Device 3 Extended Capability Structure\u003C/li>\r\n\u003Cli>Shadow Functions Extended Capability Structure\u003C/li>\r\n\u003Cli>Power Budgeting new features\u003C/li>\r\n\u003C/ul>",true,"PCIe 6.x/7 Update Course","PCIe 6.x/7.0 Update Training","PCIe 6.x/7.0 Update Training, PCIe 7.0 Training, PCIe6 Course, PCIe6 Update Course, PCI Express 6.0 Training Course","1pm-4:30pm US Pacific Time Daily","\u003Cul>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">PDF of course slides\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">\u003Ca href=\"../../elearning-course/pcie6-update-elearning-course\">PCIe6 Update eLearning course\u003C/a>\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">PCIe 6.x/7.0 Update eLearning course (when available in Q3, 2026)\u003C/span>\u003C/li>\r\n\u003C/ul>",false,{"data":28,"links":100,"meta":103},[29,46,62,81,82],{"id":30,"name":31,"slug":32,"location":7,"start_date_secondary":33,"start_date":34,"end_date_secondary":35,"end_date":36,"format":12,"price":13,"image":37,"details":38,"duration":16,"instructor":39,"prerequisites":40,"outline":41,"visible":20,"meta_title":42,"meta_description":42,"meta_keywords":43,"time":44,"training_materials":45,"button_mode":26},1,"DRAM (DDR5/LPDDR5) - 8 Half-Day Course","dram-public-class-020227","02/08/27","02/02/27","02/11/27","02/05/27","https://mindshare-prod.s3.amazonaws.com/public/public-classes/images/h7Tjg9ee7hPn_dram_public.png","\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Whether you are new to DRAM or an industry veteran seeking the latest and greatest standards, you will learn more than you expect from MindShare's DRAM courses. You may be well-versed on modern serial protocols but learning parallel-bus protocols of DDR DRAM will be valuable. You might have worked extensively with mainstream PC DRAMs and now you need to learn low-power LP DRAM designs. Any time your work requires you to design, develop, validate, verify, test, debug or support DRAM interfaces, you should seriously consider taking MindShare's classes.\u003C/span>\u003C/p>","John Swindle","\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">General understanding of digital logic, computer architecture and DRAM architecture fundamentals.\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli>System Architecture\r\n\u003Cul>\r\n\u003Cli>PC Platform Architecture\u003C/li>\r\n\u003Cli>NUMA Architecture\u003C/li>\r\n\u003Cli>SoC Architecture\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Back to the Future DRAM Intro\r\n\u003Cul>\r\n\u003Cli>It's more similar than it is different\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>DRAM Cell Architecture\r\n\u003Cul>\r\n\u003Cli>Problems of Activation, Precharge and Refresh\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>DRAM Device Architecture\r\n\u003Cul>\r\n\u003Cli>SDRAM thru DDR5\u003C/li>\r\n\u003Cli>DDR4/DDR5 Bank Groups\u003C/li>\r\n\u003Cli>LPDDR4 and LPDDR5\u003C/li>\r\n\u003Cli>LPDDR5 Bank Groups\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Packaging\r\n\u003Cul>\r\n\u003Cli>Monolithic\u003C/li>\r\n\u003Cli>Stacked Die\u003C/li>\r\n\u003Cli>WideIO Stack\u003C/li>\r\n\u003Cli>3DS, Hybrid Memory Cube, High Bandwidth Memory (HBM)\u003C/li>\r\n\u003Cli>Package-on-Package\u003C/li>\r\n\u003Cli>Dual LPDDR4 Channels\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>DRAM Controller Basics\r\n\u003Cul>\r\n\u003Cli>Functional Blocks\u003C/li>\r\n\u003Cli>Address Translation/Address Mapping Examples\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Device and Dual In-Line Memory Module (DIMM) Pin Descriptions\r\n\u003Cul>\r\n\u003Cli>DDR4\u003C/li>\r\n\u003Cli>DIMM\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Introduction to DIMM Architecture\r\n\u003Cul>\r\n\u003Cli>UDIMM\u003C/li>\r\n\u003Cli>RDIMM\u003C/li>\r\n\u003Cli>LRDIMM\u003C/li>\r\n\u003Cli>Fly-by-Routing\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Bank State Machines, Commands, Waveforms\r\n\u003Cul>\r\n\u003Cli>DDR4\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Refresh\r\n\u003Cul>\r\n\u003Cli>Auto Refresh\u003C/li>\r\n\u003Cli>Self Refresh\u003C/li>\r\n\u003Cli>Auto Self Refresh\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Device and DIMM Pin Descriptions\r\n\u003Cul>\r\n\u003Cli>DDR5\u003C/li>\r\n\u003Cli>DIMM\u003C/li>\r\n\u003Cli>LPDDR4\u003C/li>\r\n\u003Cli>LPDDR5\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>DDR4 and DDR5 DIMM Architecture\r\n\u003Cul>\r\n\u003Cli>UDIMM\u003C/li>\r\n\u003Cli>RDIMM\u003C/li>\r\n\u003Cli>LRDIMM\u003C/li>\r\n\u003Cli>NVDIMM\u003C/li>\r\n\u003Cli>PMIC\u003C/li>\r\n\u003Cli>DDR4 On-DIMM Address Mirroring\u003C/li>\r\n\u003Cli>DDR5 Mirroring\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Bank State Machines, Commands, Waveforms\r\n\u003Cul>\r\n\u003Cli>DDR5\u003C/li>\r\n\u003Cli>LPDDR4\u003C/li>\r\n\u003Cli>LPDDR5\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Newer Forms of Refresh\r\n\u003Cul>\r\n\u003Cli>Per-Bank and Fine Granularity Refresh\u003C/li>\r\n\u003Cli>Temperature Compensated Refresh\u003C/li>\r\n\u003Cli>Self-Refresh Abort, Fast Exit\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Electrical Specifications\r\n\u003Cul>\r\n\u003Cli>DDR4/DDR5 POD\u003C/li>\r\n\u003Cli>LPDDR4/LPDDR5 LVSTL\u003C/li>\r\n\u003Cli>IDD Specifications, Example\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Power Management\r\n\u003Cul>\r\n\u003Cli>Power Down and Self Refresh\u003C/li>\r\n\u003Cli>DDR4/DDR5 Max Power Saving Mode\u003C/li>\r\n\u003Cli>LPDDR4/LPDDR5 Frequency Setpoints (FSP)\u003C/li>\r\n\u003Cli>LPDDR5 Dynamic Voltage and Frequency Scaling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Introduction to Signal Integrity Issues\r\n\u003Cul>\r\n\u003Cli>Sources and Solutions\u003C/li>\r\n\u003Cli>Derating and Margining\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>On-Die Termination\r\n\u003Cul>\r\n\u003Cli>Sync/Async ODT\u003C/li>\r\n\u003Cli>DDR4/DDR5 Dynamic ODT\u003C/li>\r\n\u003Cli>LPDDR4 Data Group ODT and Command Bus ODT\u003C/li>\r\n\u003Cli>DDR4/DDR5 Park Mode\u003C/li>\r\n\u003Cli>DDR5 Command Bus ODT\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Initialization, Calibration, and Training\r\n\u003Cul>\r\n\u003Cli>JEDEC Initialization\r\n\u003Cul>\r\n\u003Cli>DDR4, DDR5 Mode Registers\u003C/li>\r\n\u003Cli>DDR4, DDR5 Initialization\u003C/li>\r\n\u003Cli>LPDDR4, LPDDR5 Mode Registers\u003C/li>\r\n\u003Cli>LPDDR4, LPDDR5 Initialization\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Calibration and Training\r\n\u003Cul>\r\n\u003Cli>ZQ Calibration\u003C/li>\r\n\u003Cli>InternalVref Training\u003C/li>\r\n\u003Cli>CA Command Bus Training\u003C/li>\r\n\u003Cli>Read Calibration\r\n\u003Cul>\r\n\u003Cli>Including Duty Cycle Adjustment\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Write Calibration\r\n\u003Cul>\r\n\u003Cli>Including DFE, FIFO, DQS Oscillator and Loopback\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Write Leveling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Errors and Error Handling\r\n\u003Cul>\r\n\u003Cli>Sources of Errors\u003C/li>\r\n\u003Cli>DIMM ECC\u003C/li>\r\n\u003Cli>DDR5 On-Die ECC\u003C/li>\r\n\u003Cli>DIMM Parity\u003C/li>\r\n\u003Cli>DDR4 CA Parity\u003C/li>\r\n\u003Cli>DDR4 Write CRC\u003C/li>\r\n\u003Cli>DDR5 Read/Write CRC\u003C/li>\r\n\u003Cli>LPDDR5 Link ECC\u003C/li>\r\n\u003Cli>MR Readout via Multi-Purpose Register\u003C/li>\r\n\u003Cli>Row Hammer and Target Row Refresh\u003C/li>\r\n\u003Cli>Post Package Repair\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Testing\r\n\u003Cul>\r\n\u003Cli>DRAM Functional Tests\u003C/li>\r\n\u003Cli>Structural Test Example\u003C/li>\r\n\u003Cli>Cell Test Example\u003C/li>\r\n\u003Cli>DRAM Parametric (pin) Tests\u003C/li>\r\n\u003Cli>DDR4 Connectivity Test Mode\u003C/li>\r\n\u003Cli>DDR5 Loopback Mode\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","DRAM DDR5/LPDDR5 Training","DRAM Training, DDR5 Training, LPDDR5 Training, DRAM Course, DDR5 Course, LPDDR5 Course, DRAM Course","1:30pm - 5pm US Pacific Time","\u003Cul>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">PDF of course slides\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">\u003Ca href=\"../../elearning-course/modern-dram-ddr5-ddr4-lpddr5-lpddr4-elearning-course\">Modern DRAM eLearning Course\u003C/a>\u003C/span>\u003C/li>\r\n\u003C/ul>",{"id":47,"name":48,"slug":49,"location":7,"start_date_secondary":50,"start_date":51,"end_date_secondary":52,"end_date":53,"format":12,"price":13,"image":54,"details":55,"duration":16,"instructor":39,"prerequisites":56,"outline":57,"visible":20,"meta_title":58,"meta_description":58,"meta_keywords":59,"time":60,"training_materials":61,"button_mode":26},134,"High Bandwidth Memory (Up to HBM4E) - 8-Half-Day Course","hbm-public-class-021627","02/22/27","02/16/27","02/25/27","02/19/27","https://mindshare-prod.s3.amazonaws.com/public/public-classes/images/yFdmz9yQzRQH_HBM%20Public%20Class%20Thumbnail.png","\u003Cp>High Bandwidth Memory (HBM) is a form of DRAM used on the most capable HPC and SoC platforms. HBM is an evolution of WideIO and WideIO2 with some concepts borrowed from Graphics DRAM. HBM provides the maximum possible bandwidth of any DRAM technology, largely by implementing several very wide channels. All DRAM (PC DRAM, LP DRAM, Graphics DRAM, HBM) are very similar to one another, but there are significant differences in HBM that this course covers in detail. Our course describes HBM architecture up to HBM4E.\u003C/p>","\u003Cp> Digital design and computer architecture background.\u003C/p>","\u003Cp>\u003Cstrong>DRAM Fundamentals - Half-Day 1-2\u003C/strong>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>System Architecture and Intro to DRAM\u003C/li>\r\n\u003Cli>DRAM Device Architecture\u003C/li>\r\n\u003Cli>Packaging and HBM\u003C/li>\r\n\u003Cli>DRAM Controller Basics and Addresses\u003C/li>\r\n\u003Cli>DDR4 Device and Pin Descriptions\u003C/li>\r\n\u003Cli>Signal Routing\u003C/li>\r\n\u003Cli>DDR4 - Bank State Machines, Commands and Waveforms\u003C/li>\r\n\u003Cli>Refresh\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cstrong>HBM Topics - Half-Day 3-8\u003C/strong>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>System Architecture and Packaging\r\n\u003Cul>\r\n\u003Cli>Example Platforms\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Channel Architecture, Device Organization and Device Architecture\r\n\u003Cul>\r\n\u003Cli>Features and Architectures of Previous Technologies (PC and LP DRAMs)\u003C/li>\r\n\u003Cli>HBM Channels and Pseudo channels\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Signal Descriptions\r\n\u003Cul>\r\n\u003Cli>Channel Signals\u003C/li>\r\n\u003Cli>Global Signals\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Bank State Machines, Commands and Waveforms\r\n\u003Cul>\r\n\u003Cli>Simultaneous Row and Column Commands\u003C/li>\r\n\u003Cli>Use of WDQS and RDQS\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Refresh\r\n\u003Cul>\r\n\u003Cli>Auto Refresh\u003C/li>\r\n\u003Cli>Self Refresh\u003C/li>\r\n\u003Cli>Single-bank (Per-bank) Refresh\u003C/li>\r\n\u003Cli>Row Hammer, Target Row Refresh and Refresh Management\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Electrical Specifications\r\n\u003Cul>\r\n\u003Cli>Why so many traditional SI tools (ODT, ZQ cal, etc.) are not present\u003C/li>\r\n\u003Cli>IDD Specification\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Power Management\r\n\u003Cul>\r\n\u003Cli>Power Down\u003C/li>\r\n\u003Cli>Clock Throttling\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Initialization, Calibration, and Training\r\n\u003Cul>\r\n\u003Cli>JEDEC Initialization\r\n\u003Cul>\r\n\u003Cli>Mode Registers\u003C/li>\r\n\u003Cli>Initialization Steps\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Calibration and Training\r\n\u003Cul>\r\n\u003Cli>Vref Training\u003C/li>\r\n\u003Cli>Loopback LFSR MISR Training\r\n\u003Cul>\r\n\u003Cli>Command Bus (AWORD) Training\u003C/li>\r\n\u003Cli>Data Group (DWORD) Training\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Duty Cycle Adjustment (DCA) and Duty Cycle Monitoring (DCM)\u003C/li>\r\n\u003Cli>WDQS Interval Oscillator\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Errors and Error Handling\r\n\u003Cul>\r\n\u003Cli>Temperature\u003C/li>\r\n\u003Cli>Address Parity\u003C/li>\r\n\u003Cli>Data Parity\u003C/li>\r\n\u003Cli>Channel Remapping\u003C/li>\r\n\u003Cli>Sideband ECC\u003C/li>\r\n\u003Cli>On-Die ECC\u003C/li>\r\n\u003Cli>Post Package Repair\r\n\u003Cul>\r\n\u003Cli>Self-Repair\u003C/li>\r\n\u003Cli>Hard and Soft Repair\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli>Overview of IEEE 1500\u003C/li>\r\n\u003C/ul>","HBM4E Training","HBM Training, HBM4 Training, HBM4E Training, High Bandwidth Memory Architecture Course, HBM Course, Memory Architecture Training","1pm - 4:30pm US Pacific Time Daily","\u003Cul>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">PDF of course slides\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">HBM4E Architecture eLearning\u003C/span>\u003C/li>\r\n\u003C/ul>",{"id":63,"name":64,"slug":65,"location":7,"start_date_secondary":66,"start_date":67,"end_date_secondary":68,"end_date":69,"format":12,"price":70,"image":71,"details":72,"duration":73,"instructor":74,"prerequisites":75,"outline":76,"visible":20,"meta_title":77,"meta_description":78,"meta_keywords":79,"time":24,"training_materials":80,"button_mode":26},135,"PCI Express (PCIe) 5.0 - 10-Half-Day Course","pcie-public-class-030127","03/08/27","03/01/27","03/12/27","03/05/27","3495.00","https://mindshare-prod.s3.amazonaws.com/public/public-classes/images/agtnbyyjFA27_PCIe5.png","\u003Cp>MindShare's PCI Express System Architecture course starts with a high-level view of the technology to provide the big-picture context and then drills down into the details for each topic, providing a thorough understanding of the hardware and software protocols.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>The course describes additional features added to the architecture when moving through the PCIe specification revisions from 1.1 all the way to the latest 6.2. There are a large number of features and optional behaviors described in the PCIe spec. MindShare can customize the course to cover the topics that are most important for your group. Use the course outline below as a guide to request topics you want covered or removed. The table below contains a list of suggested course customizations.\u003C/p>","10 half-days","Mike Jackson","\u003Cp>A good understanding of basic computer architecture and serial bus architecture. It will help to have some exposure to PCI Express but not a requirement.\u003C/p>","\u003Cp>\u003Cstrong>Topics Below Are To Be Covered Via MindShare's PCIe Fundamentals eLearning Mandatory Self-Study Prework\u003C/strong>\u003C/p>\r\n\u003Cul>\r\n\u003Cli>PCI Architecture Background Foundation\r\n\u003Cul>\r\n\u003Cli class=\"p1\">PCI concepts important for understanding PCI Express\u003C/li>\r\n\u003Cli class=\"p1\">Physical Address Spaces\u003C/li>\r\n\u003Cli class=\"p1\">Traffic Types (System Memory, PIO and DMA)\u003C/li>\r\n\u003Cli class=\"p1\">Typical System Transactions (NVMe Example)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">PCI Express Features and Architecture Overview\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Layered Architecture\u003C/li>\r\n\u003Cli class=\"p1\">ARM example topology\u003C/li>\r\n\u003Cli class=\"p1\">TLP, DLLP and Ordered Set Packet Format Overview\u003C/li>\r\n\u003Cli class=\"p1\">Protocol Overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Configuration Overview\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Legacy and Enhanced Configuration Access Mechanism (ECAM)\u003C/li>\r\n\u003Cli class=\"p1\">Type 0 and Type 1 Headers, Capability and Extended Capability Structures\u003C/li>\r\n\u003Cli class=\"p1\">Bus Enumeration\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Address Space and Transaction Routing\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Clarification of Memory space\u003C/li>\r\n\u003Cli class=\"p1\">System memory vs MMIO\u003C/li>\r\n\u003Cli class=\"p1\">Prefetchable vs Non-prefetchable\u003C/li>\r\n\u003Cli class=\"p1\">IO space\u003C/li>\r\n\u003Cli class=\"p1\">Setting up the BARs as well as the Base and Limit registers\u003C/li>\r\n\u003Cli class=\"p1\">Switch Routing Mechanism\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>\u003Cstrong>Topics Below Are Covered In Class\u003C/strong>\u003C/p>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">TLP Format Details\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Normal TLP fields\u003C/li>\r\n\u003Cli class=\"p1\">TLP Prefixes\u003C/li>\r\n\u003Cli class=\"p1\">10-bit Tags\u003C/li>\r\n\u003Cli class=\"p1\">PCI-SIG Vendor-Defined Messages\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Flow Control\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Flow Control Protocol\u003C/li>\r\n\u003Cli class=\"p1\">Scaled Flow Control\u003C/li>\r\n\u003Cli class=\"p1\">Link Feature Exchange\u003C/li>\r\n\u003Cli class=\"p1\">Flow Control Initialization\u003C/li>\r\n\u003Cli class=\"p1\">Runtime Flow Control Update Mechanism\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Transaction Ordering\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Simplified Ordering Table overview\u003C/li>\r\n\u003Cli class=\"p1\">Relaxed and ID-Based Ordering overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">DLLP Format Details\r\n\u003Cul>\r\n\u003Cli class=\"p1\">DLLPs\u003C/li>\r\n\u003Cli class=\"p1\">NOP & Data Link Feature DLLPs\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">ACK / NAK Protocol\r\n\u003Cul>\r\n\u003Cli class=\"p1\">TLP Error Recovery Mechanism\u003C/li>\r\n\u003Cli class=\"p1\">Simplified Replay Timer\u003C/li>\r\n\u003Cli class=\"p1\">Examples of Numerous Error Scenarios\u003C/li>\r\n\u003Cli class=\"p1\">Nullified Packets and Cut-Through Mode Switches\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Physical Layer Logic (2.5GT/s and 5.0GT/s)\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Block Diagram\u003C/li>\r\n\u003Cli class=\"p1\">Ordered Sets\u003C/li>\r\n\u003Cli class=\"p1\">Byte Striping/Unstriping\u003C/li>\r\n\u003Cli class=\"p1\">Scrambling/Unscambling\u003C/li>\r\n\u003Cli class=\"p1\">8b/10b Encoding/Decoding\u003C/li>\r\n\u003Cli class=\"p1\">Serializing/Deserializing\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Physical Layer Logic (8.0GT/s, 16.0GT/s and 32.0GT/s)\r\n\u003Cul>\r\n\u003Cli class=\"p1\">128b/130b Encoding/Decoding\u003C/li>\r\n\u003Cli class=\"p1\">Control SKPs\u003C/li>\r\n\u003Cli class=\"p1\">Ordered-Set Blocks and Data Blocks\u003C/li>\r\n\u003Cli class=\"p1\">Data Streams and Packet Framing\u003C/li>\r\n\u003Cli class=\"p1\">Precoding\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Physical Layer Electrical (all speeds)\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Differential Tx / Rx\u003C/li>\r\n\u003Cli class=\"p1\">2.5GT/s and 5.0GT/s De-emphasis\u003C/li>\r\n\u003Cli class=\"p1\">8.0GT/s, 16.0GT/s and 32.0GT/s Equalization Concept\u003C/li>\r\n\u003Cli class=\"p1\">Rx Equalization overview\u003C/li>\r\n\u003Cli class=\"p1\">Spread Spectrum Clocking (SSC) overview\u003C/li>\r\n\u003Cli class=\"p1\">Separate Refclk Independent SSC (SRIS) overview\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Link Initialization and Training (LTSSM)\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Detect, Polling, Configuration, L0 States\u003C/li>\r\n\u003Cli class=\"p1\">Recovery: Link Speed Change\u003C/li>\r\n\u003Cli class=\"p1\">Recovery: Equalization Process\u003C/li>\r\n\u003Cli class=\"p1\">16.0 GT/s Equalization and Config Structures\u003C/li>\r\n\u003Cli class=\"p1\">Negotiation for skipping parts or all of Tx Equalization\u003C/li>\r\n\u003Cli class=\"p1\">32.0 GT/s Equalization and Config Structures\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Error Detection and Handling\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Correctable, Non-Fatal and Fatal Errors\u003C/li>\r\n\u003Cli class=\"p1\">Advisory Non-Fatal Errors\u003C/li>\r\n\u003Cli class=\"p1\">Advanced Error Reporting (AER)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">System Resets\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Conventional Reset Mechanisms: Cold, Warm and Hot Reset\u003C/li>\r\n\u003Cli class=\"p1\">Function Level Reset (FLR)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">1b/1b Physical Layer (PCIe 6.0)\r\n\u003Cul>\r\n\u003Cli class=\"p1\">PAM4\u003C/li>\r\n\u003Cli class=\"p1\">Precoding, Gray Coding and Forward Error Correction (FEC)\u003C/li>\r\n\u003Cli class=\"p1\">LTSSM Updates (TS0s, Tx EQ changes, entering Flit Mode, etc.)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">Flit Mode\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Flit Format\u003C/li>\r\n\u003Cli class=\"p1\">Error Correction and Flit Retry (Standard vs Selective)\u003C/li>\r\n\u003Cli class=\"p1\">DLP Bytes in Flit and Flit Types\u003C/li>\r\n\u003Cli class=\"p1\">Flow Control (Dedicated vs Shared)\u003C/li>\r\n\u003Cli class=\"p1\">TLP Structure (Header Base, OHC, TLP Trailer, etc.)\u003C/li>\r\n\u003Cli class=\"p1\">Segments\u003C/li>\r\n\u003Cli class=\"p1\">L0p\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","PCIe 5.0 Architecture","PCIe 5.0 Architecture Training","PCIe 5.0 Architecture Training, PCIe 5.0 Course, PCI Express 5.0 Training, PCI Express 5.0 Architecture Training","\u003Cul>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">PDF of course slides\u003C/span>\u003C/li>\r\n\u003Cli>\"\u003Ca href=\"../../ebook/pci-express-technology-30\">PCI Express Technology\u003C/a>\" eBook (covers up to PCIe 3.0)\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">\u003Ca href=\"../../elearning-course/pcie5-elearning-course\">PCI Express 5.0 eLearning course\u003C/a>\u003C/span>\u003C/li>\r\n\u003C/ul>",{"id":4,"name":5,"slug":6,"location":7,"start_date_secondary":8,"start_date":9,"end_date_secondary":10,"end_date":11,"format":12,"price":13,"image":14,"details":15,"duration":16,"instructor":17,"prerequisites":18,"outline":19,"visible":20,"meta_title":21,"meta_description":22,"meta_keywords":23,"time":24,"training_materials":25,"button_mode":26},{"id":83,"name":84,"slug":85,"location":86,"start_date_secondary":87,"start_date":88,"end_date_secondary":89,"end_date":90,"format":12,"price":70,"image":91,"details":92,"duration":73,"instructor":93,"prerequisites":94,"outline":95,"visible":20,"meta_title":96,"meta_description":97,"meta_keywords":98,"time":24,"training_materials":99,"button_mode":26},2,"Compute Express Link (CXL) 3.0 - 10-Half-Day Course","cxl-public-class-032927","Virtual-Classroom","04/05/27","03/29/27","04/09/27","04/02/27","https://mindshare-prod.s3.amazonaws.com/public/public-classes/images/Hyqhw7l2IbTc_cxl_public.png","\u003Cp>Compute Express Link (CXL) is a high-bandwidth, low-latency serial bus interconnect between host processors and devices such as accelerators, memory controllers/buffers, and I/O devices. CXL 3.0 is based on PCI Express (PCIe) 6.0 physical layer running at 64 GT/s with x16, x8 and x4 link widths. Degraded modes run at 32 GT/s, 16 GT/s and 8 GT/s with x2 and x1 link widths.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>CXL interconnect adds coherency and memory semantics, thus allowing for its application in heterogeneous processing systems with a variety of host processors, memory subsystems and peripheral devices interconnected. CXL has applications in standard computer systems, Artificial Intelligence (AI), Machine Learning, communication systems, and High-Performance Computing (HPC). Emerging applications require a diverse mix of CPUs, GPUs, FPGAs, peripherals such as smart NICs, and other accelerators interconnected via an open industry standard protocol with the necessary features which CXL provides. CXL provides a rich set of three protocols that include 1) CXL.io based on PCIe TLP based transactions, 2) CXL.cache and 3) CXL.mem semantics. CXL uses the PCIe stack offering full interoperability with PCIe. CXL.cachemem protocols allow for coherent transactions in memory space. These transactions employ Flit-based packet routing on the Link.\u003C/p>\r\n\u003Cp> \u003C/p>\r\n\u003Cp>MindShare’s comprehensive CXL 3.0 Architecture course provides a solid foundation of platform architectures and use cases of the three CXL protocols with Type 1, Type 2 and Type 3 devices in platform example. The course details the role of the Transaction Layer protocol, Link Layer including Flit packing and unpacking, ARB/MUX and Flex Bus Logical and Electrical Physical Layer of a CXL port design. We explain enumeration and configuration process during system bring-up with details of configuration and component registers. Other topics include switch architecture, reset, manageability, RAS features, power management, performance considerations and compliance testing. The course describes new features added to the CXL 3.0 spec such as 256B and Port Based Routing (PBR) Flits, CXL.mem Back-Invalidation, Dynamic Capacity Devices (DCD), LD-FAM and G-FAM Devices, Global Integrated Memory (GIM), Multi-Headed (MH) Devices, Hierarchy Based Routing (HBR) and Port Based Routing (PBR), Direct Peer-to-Peer Routing and lots more.\u003C/p>","Ravi Budruk","\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0); font-size: 12pt;\">Complete working knowledge of PCI Express architecture. Computer architecture fundamentals. Cache coherency concepts incuding MESI protocol\u003C/span>\u003C/p>","\u003Cul>\r\n\u003Cli class=\"p1\">\u003Cstrong>CXL Features and Architecture Overview\u003C/strong>\r\n\u003Cul>\r\n\u003Cli>CXL 1.1, CXL 2.0 and CXL 3.0 Features\u003C/li>\r\n\u003Cli>CXL.mem, CXL.cache and CXL.io\u003C/li>\r\n\u003Cli>Type 1 (with cache), Type 2 (with cache and memory, Type 3 (with memory) Devices\u003C/li>\r\n\u003Cli>Switch and MLD device architecture overview\u003C/li>\r\n\u003Cli>CXL 3.0 features overview\u003C/li>\r\n\u003Cli>Layered architecture overview\u003C/li>\r\n\u003Cli>Transaction flows in platforms with PCIe, CXL Type 1, 2, 3 Devices\u003C/li>\r\n\u003Cli>Cache coherency and MESI protocol tutorial\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>Transaction Layer\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">CXL.mem protocol\u003C/li>\r\n\u003Cli class=\"p1\">CXL.cache protocol\u003C/li>\r\n\u003Cli class=\"p1\">CXL.mem back-invalidation and CXL.cache device scaling\u003C/li>\r\n\u003Cli class=\"p1\">CXL.io protocol PTH and UIO Ordering Rules\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>Link Layer\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">IO Flit Packing\u003C/li>\r\n\u003Cli class=\"p1\">Cache/Mem Flit Packing\u003C/li>\r\n\u003Cli class=\"p1\">Control Flits\u003C/li>\r\n\u003Cli class=\"p1\">68B Flits 256B and PBR Flits\u003C/li>\r\n\u003Cli class=\"p1\">Cachemem Link Layer Retry (LLR) mechanism\u003C/li>\r\n\u003Cli class=\"p1\">Flow Control\u003C/li>\r\n\u003Cli class=\"p1\">Viral Feature\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>ARB/Mux Layer\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Arbitration and Flit Multiplexing/DeMuxing\u003C/li>\r\n\u003Cli class=\"p1\">vLSM and Link Power Management\u003C/li>\r\n\u003Cli class=\"p1\">ALMP Flits\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>Physical Layer\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Protocol ID\u003C/li>\r\n\u003Cli class=\"p1\">Flit Header\u003C/li>\r\n\u003Cli class=\"p1\">NOP Flits, IDLE Flits, Latency Optimized Flits\u003C/li>\r\n\u003Cli class=\"p1\">CRC, FEC\u003C/li>\r\n\u003Cli class=\"p1\">Synch Header Bypass\u003C/li>\r\n\u003Cli class=\"p1\">1b/1b encoding \u003C/li>\r\n\u003Cli class=\"p1\">Link Training\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">\u003Cstrong>Reset\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Cold reset\u003C/li>\r\n\u003Cli class=\"p1\">Warm reset\u003C/li>\r\n\u003Cli class=\"p1\">Hot reset\u003C/li>\r\n\u003Cli class=\"p1\">CXL reset\u003C/li>\r\n\u003Cli class=\"p1\">Function Level reset (FLR)\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>Power Management\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Runtime control PM\u003C/li>\r\n\u003Cli class=\"p1\">Physical Layer PM\u003C/li>\r\n\u003Cli class=\"p1\">CXL.io PM\u003C/li>\r\n\u003Cli class=\"p1\">CXL.cachemem PM\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>RAS and Error Handling\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">EFN Message\u003C/li>\r\n\u003Cli class=\"p1\">Viral Handling\u003C/li>\r\n\u003Cli class=\"p1\">Error Logging\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>Enumeration and Manageability\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Enumeration in 1.1 and 2.0 Platforms\u003C/li>\r\n\u003Cli class=\"p1\">Memory Interleaving Memory Interleaving in CXL 3.0\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003Cli class=\"p1\">\u003Cstrong>Control and Status Registers\u003C/strong>\r\n\u003Cul>\r\n\u003Cli class=\"p1\">Configuration registers and DVSEC Component Registers\u003C/li>\r\n\u003Cli class=\"p1\">Backwards compatibiity to CXL 1.1\u003C/li>\r\n\u003Cli class=\"p1\">CXL 3.0 registers\u003C/li>\r\n\u003C/ul>\r\n\u003C/li>\r\n\u003C/ul>","CXL Training","CXL 3.0 Training","CXL Architecture Training, CXL 3.0 Training, CXL Course, Compute Express Link Training, CXL 3.0 Training Course","\u003Cul>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">PDF of course slides\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">\"\u003Ca href=\"../../ebook/pci-express-technology-30\">PCI Express Technology\u003C/a>\" eBook (covers PCIe 3.0)\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\u003Cspan style=\"font-size: 12pt;\">\u003Ca href=\"../../elearning-course/comprehensive-cxl-20-elearning-course\">CXL 2.0 eLearning Course\u003C/a>\u003C/span>\u003C/li>\r\n\u003Cli style=\"font-size: 12pt;\">\r\n\u003Cdiv>\u003Cspan style=\"font-size: 12pt;\">\u003Ca href=\"../../elearning-course/cxl-31-update-elearning-course\">CXL 3.0 Update eLearning Course\u003C/a>\u003C/span>\u003C/div>\r\n\u003C/li>\r\n\u003C/ul>",{"first":101,"last":101,"prev":102,"next":102},"https://mindshare.com/api/public-class/visible-future?page=1",null,{"current_page":30,"from":30,"last_page":30,"links":104,"path":111,"per_page":112,"to":113,"total":113},[105,107,109],{"url":102,"label":106,"active":26},"« Previous",{"url":101,"label":108,"active":20},"1",{"url":102,"label":110,"active":26},"Next »","https://mindshare.com/api/public-class/visible-future",20,5,1793374155813]