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Fundamentals of DRAM
Instructor(s): John Swindle
Number of Modules: 23
Subscription Length: 90 days
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Course Price
$595.00 |
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Fundamentals of DRAM eLearning Course Info
Note: This course is a subset of the comprehensive course entitled Modern DRAM (DDR5 / DDR4 / LPDDR5 / LPDDR4).
If you purchase this fundamentals course and then want to upgrade to the comprehensive course, you will only have to pay the difference for the upgrade.
What's Included?
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DRAM eLearning modules
(unlimited access for 90 days) |
PDF of Course Slides
(yours to keep, does not expire) |
Benefits of eLearning:
- Cost Effective - Get the same information delivered in a live MindShare class at a fraction of the cost
- Available 24/7 - MindShare eLearning courses are available when and where you need them
- Learn at Your Pace - MindShare eLearning courses are self-paced, so you can proceed when you're ready
- Access to the Instructor - Ask questions to the MindShare Instructor that taught the course
You Will Learn:
- Where JEDEC expects DRAM to appear in a system
- How a DRAM cell is addressed by the controller
- Difference between Banks, Bank Groups and Ranks
- Why the DRAM controller is so complicated
- Activation, Precharge and Refresh
- DDR4 pin definitions
- DDR4 bank state diagram
- DDR4 timing waveforms
- Prefetch Width
- Types of DIMMS
- Fly-By Routing
- PC and LP DRAM device architectures and features including DDR5 and LPDDR5
Who Should View?
This course is hardware-centric and describes the basics of DRAM devices and controllers. It is suitable for hardware engineers and software/firmware engineers will also benefit. The course is ideal for DRAM controller designers, chipset designers, system board-level design and validation engineers. This course introduces current DRAM technologies, concentrating on DDR4 as a baseline to teach concepts that are common to all DRAMs.
Course Outline:
- Module 1: Introduction and Outline
- Intro to the course, outline and objectives
- Module 2: System Architecture
- Shows where DRAM fits in traditional and non-traditional computer systems
- Module 3: Intro to DRAM
- Discusses the history of DRAM and the pros / cons of DRAM vs SRAM, also describes DRAM cell architecture
- Modules 4a-4e: DRAM Device Architecture
- Shows how the evolution of DRAM arrays and banks which leads into addressing data within a DRAM array; Defines banks, ranks and channels; Walks through the evolution of DRAM architecture (SDR, DDR1, DDR2, DDR3, DDR4, DDR4 and then on to LPDDR3, LPDDR4 and LPDDR5)
- Module 5: Packaging and HBM
- Introduces different package types (BGA, PoP, 3D Stacking, Die Stacking, TSI and Hybrid Memory Cube); Provides a brief discussion of High Bandwidth Memory (HBM)
- Modules 6a-6b: DRAM Controller Basics and Addresses
- Discusses required blocks of a DRAM controller (address and control mux, refresh timer, PLL, timing generator, control registers, read and write buffer and IO buffer pads); Describes the translation necessary from system address to DRAM addressing, including symmetric vs asymmetric schemes and NUMA
- Modules 7a-7b: DDR4 Device and DIMM Pin Descriptions
- Provides a description of the DDR4 device and DIMM pin groups as well as discusses changes in the JEDEC documentation styles to help avoid confusion when reading the standards
- Modules 8a-8b: Intro to DIMMs (Dual Inline Memory Modules)
- Walks through the evolution of DIMMs from SIMMs to the various types of DIMMs (UDIMMs, RDIMMs, LRDIMMs, NVDIMMs, etc.)
- Module 9: Signal Routing
- Discusses basic signal routing rules and then walks through detailed examples of DDR4 fly-by routing for reads and writes
- Module 10a-10e: DDR4 - Bank State Machines, Commands and Waveforms
- Shows a detailed view of the DDR4 Bank States and discusses numerous state transitions, their motivations, behaviors, requirements, etc.; Contains a detailed table of DDR4 commands with descriptions; Walks through numerous DDR4 timing diagrams of various commands and provides insights for the motivations of behaviors and requirements; Also discusses burst orientations, types, lengths and order; Also discusses additive latency, NOP and power down
- Module 11a-11b: Refresh
- Provides a description of the different types of refresh and its history; Discusses important refresh timing parameters like Retention, Refresh Interval and Cycle Time; Describes the refresh command
 | Course Modules |
| Module | Length | | Module 1: Fundamentals of DRAM | 31 minutes | | Module 2: System Architecture | 33 minutes | | Module 3: Intro to DRAM | 33 minutes | | Module 4a: DRAM Device Architecture | 37 minutes | | Module 4b: DRAM Device Architecture | 27 minutes | | Module 4c: DRAM Device Architecture | 32 minutes | | Module 4d: DRAM Device Architecture | 38 minutes | | Module 4e: DRAM Device Architecture | 37 minutes | | Module 5: Packaging and HBM | 32 minutes | | Module 6a: DRAM Controller Basics and Addresses | 22 minutes | | Module 6b: DRAM Controller Basics and Addresses | 28 minutes | | Module 7a: DDR4 Device and DIMM Pin Descriptions | 39 minutes | | Module 7b: DDR4 Device and DIMM Pin Descriptions | 33 minutes | | Module 8a: Intro to DIMMs (Dual Inline Memory Modules) | 30 minutes | | Module 8b: Intro to DIMMs (Dual Inline Memory Modules) | 29 minutes | | Module 9: Signal Routing | 36 minutes | | Module 10a: DDR4 - Bank State Machines, Commands and Waveforms | 33 minutes | | Module 10b: DDR4 - Bank State Machines, Commands and Waveforms | 19 minutes | | Module 10c: DDR4 - Bank State Machines, Commands and Waveforms | 24 minutes | | Module 10d: DDR4 - Bank State Machines, Commands and Waveforms | 44 minutes | | Module 10e: DDR4 - Bank State Machines, Commands and Waveforms | 23 minutes | | Module 11a: Refresh | 36 minutes | | Module 11b: Refresh with Fundamentals of DRAM End Bump | 37 minutes | | |
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Intel Architecture
