The Unabridged Pentium 4: IA32 Processor Genealogy book provides an in-depth description and comprehensive reference to the Intel IA32 processor family. This book takes the evolutionary approach in describing the growth of the IA32 processor hardware and software architecture starting with the 386 processor and covering through the Pentium 4 with the Prescott instruction set extensions, the Pentium M and the Pentium 4 Xeon processors.

• Single Task/Multitasking OS Background
• 32-bit Register Set
• Real Mode
• Protected Mode
• Instruction Set
• Virtual 8086 Mode
• Demand Mode Paging
• Interrupts and Exceptions
• APIC Subsystem
• Evolution of the IA32 Processors
• Overview of the P6 Core
• The P6 FSB operation
• Processor Power Management
• Pentium 4 Road Map
• Pentium 4 System Overview
• Pentium 4 Processor Overview
• Pentium 4 PowerOn Configuration
• Pentium 4 Processor Startup
• Pentium 4 Core Description
• Hyper-Threading
• The Pentium 4 Caches
• Pentium 4 Handling of Loads and Stores
• The Pentium 4 Prescott
• Pentium 4 FSB Electrical Characteristics
• Intro to the Pentium 4 FSB
• Pentium 4 CPU Arbitration
• Pentium 4 Priority Agent Arbitration
• Pentium 4 Locked Transaction Series
• Pentium 4 FSB Blocking
• Pentium 4 FSB Request Phase
• Pentium 4 FSB Snoop Phase
• Pentium 4 FSB Response and Data Phases
• Pentium 4 FSB Transaction Deferral
• Pentium 4 FSB IO Transactions
• Pentium 4 FSB Central Agent Transactions
• Pentium 4 FSB Miscellaneous Signals
• Pentium 4 Software Enhancements
• Pentium 4 Xeon Features
• System Management Mode (SMM)

Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.