PCIe - PCI Express
Let MindShare Bring "PCI Express" to Life for You
PCIe - PCI Express
Duration: 4 - 5 days
Student Review:
"It was tailored to what knowledge we needed and the level at which we are working. Did not waste time investing into details that aren't relevant to our work." - Nathan (ARM)
Core PCIe eLearning Course
Fundamentals of PCI Express eLearning Course
Advanced PCIe eLearning Course
PIPE 6.0 - PHY Interface for PCI Express and more
PCIe6 Update eLearning Course
PCIe Security eLearning Course
PCIe 5.0 eLearning Course
PCI Express Technology 3.0
Core PCIe eLearning Course
Fundamentals of PCI Express eLearning Course
Advanced PCIe eLearning Course
PIPE 6.0 - PHY Interface for PCI Express and more
PCIe6 Update eLearning Course
PCIe Security eLearning Course
PCIe 5.0 eLearning Course
PCI Express Technology 3.0
Overview
MindShare's PCI Express System Architecture course starts with a high-level view of the technology to provide the big-picture context and then drills down into the details for each topic, providing a thorough understanding of the hardware and software protocols.
The course describes additional features added to the architecture when moving through the PCIe specification revisions from 1.1 all the way to the latest 6.2. There are a large number of features and optional behaviors described in the PCIe spec. MindShare can customize the course to cover the topics that are most important for your group. Use the course outline below as a guide to request topics you want covered or removed. The table below contains a list of suggested course customizations.
All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group.
What You Will Learn
- PCI Express features and capabilities
- The definition and responsibilities of each of the layers in the interface
- The PCIe packet-based transaction protocol details
- The error detection, reporting and possible correction mechanisms
- The address space and packet-routing methods used
- How the various power management techniques work
- The details of the configuration registers that provide control and status visibility to software
- Software enumeration process
- The process of transmitter equalization necessary to operate at 8.0GT/s, 16.0GT/s and 32.0GT/s
- The details of the LTSSM including the concepts important for each state
- PAM4 signaling
- Flit Mode behavior
For SRIOV and ATS related topics, which are now incorporated into the PCIe base spec, please request our 3-day IO Virtualization for Intel Platforms course or our IO Virtualization for ARM Platforms course as these topics are NOT covered in this standard 5-day PCIe course.
For PCIe Security related topics, please request our dedicated 3-day PCIe Security as these topics are NOT covered in this standard 5-day PCIe course.
PIPE related topics are also NOT covered but can be requested.
Course Outline
|
Topic
|
5-day Class PCIe 7.0 |
4-day Class PCIe 6.x / 7.0 Update |
5-day Class PCIe 5.0 |
|
| PCI Architecture Background Foundation | ||||
| PCI concepts important for understanding PCIe |
pre-class eLearning
|
X | ||
| Physical Address Spaces | X | |||
| Traffic Types (System Memory, PIO and DMA) | X | |||
| Typical System Transactions (NVMe Example) | X | |||
| PCI Express Features and Architecture Overview | ||||
| Layered Architecture |
pre-class eLearning
|
X | ||
| ARM example topology | X | |||
| TLP, DLLP and Ordered Set Packet Format Overview | X | |||
| Protocol Overview | X | |||
| Configuration Overview | ||||
| Legacy and Enhanced Configuration Access Mechanism (ECAM) |
pre-class eLearning
|
X | ||
| Type 0 and Type 1 Headers, Capability and Extended Capability Structures | X | |||
| Bus Enumeration | refresher | X | ||
| Address Space and Transaction Routing | ||||
| Clarification of Memory space |
pre-class eLearning
|
X | ||
| System memory vs MMIO | X | |||
| Prefetchable vs Non-prefetchable | X | |||
| IO space | X | |||
| Setting up the BARs as well as the Base and Limit registers | X | |||
| Switch Routing Mechanism | X | |||
| TLP Format Details | ||||
| Normal TLP fields | X | refresher | X | |
| TLP Prefixes | X | X | ||
| 10-bit Tags | X | X | ||
| PCI-SIG Vendor-Defined Messages | X | X | ||
| Quality of Service and Arbitration | ||||
| TC/VC Mapping | overview | |||
| VC Arbitration | overview | |||
| Port Arbitration | overview | |||
| Multi-function Arbitration | overview | |||
| Flow Control | ||||
| Flow Control Protocol | X | refresher | X | |
| Scaled Flow Control | X | X | ||
| Link Feature Exchange | X | X | ||
| Flow Control Initialization | X | X | ||
| Runtime Flow Control Update Mechanism | X | X | ||
| Transaction Ordering | ||||
| Simplified Ordering Table | overview | X | ||
| Relaxed and ID-Based Ordering | overview | X | ||
| DLLP Format Details | ||||
| DLLPs | X | X | ||
| NOP & Data Link Feature DLLPs | X | refresher | X | |
| ACK / NAK Protocol | ||||
| TLP Error Recovery Mechanism | X | refresher | X | |
| Simplified Replay Timer | X | X | ||
| Examples of Numerous Error Scenarios | X | X | ||
| Nullified Packets and Cut-Through Mode Switches | X | X | ||
| Physical Layer Logic (2.5GT/s and 5.0GT/s) | ||||
| Block Diagram | X | X | ||
| Ordered Sets | X | refresher | X | |
| Byte Striping/Unstriping | X | X | ||
| Scrambling/Unscambling | X | X | ||
| 8b/10b Encoding/Decoding | X | X | ||
| Serializing/Deserializing | X | X | ||
| Physical Layer Logic (8.0GT/s, 16.0GT/s and 32.0GT/s) | ||||
| 128b/130b Encoding/Decoding | X | X | ||
| Control SKPs | X | X | ||
| Ordered-Set Blocks and Data Blocks | X | X | ||
| Data Streams and Packet Framing | X | X | ||
| Data Parity Checking | X | |||
| 16.0 & 32.0 GT/s Data Parity Checking | X | |||
| Precoding | X | X | ||
| Physical Layer Electrical (all speeds) | ||||
| Differential Tx / Rx | X | X | ||
| 2.5GT/s and 5.0GT/s De-emphasis | X | X | ||
| 8.0GT/s, 16.0GT/s and 32.0GT/s Equalization Concept | X | refresher | X | |
| Rx Equalization | overview | X | ||
| Electrical Conditions for different Link States | X | |||
| Spread Spectrum Clocking (SSC) | overview | X | ||
| Separate Refclk Independent SSC (SRIS) | overview | X | ||
| Link Initialization and Training (LTSSM) | ||||
| Detect, Polling, Configuration, L0 States | X | refresher | X | |
| Recovery: Link Speed Change | X | X | ||
| Recovery: Equalization Process | X | X | ||
| 16.0 GT/s Equalization and Config Structures | X | X | ||
| Negotiation for skipping parts or all of Tx Equalization | X | X | ||
| 32.0 GT/s Equalization and Config Structures | X | X | ||
| Recovery: Link Width Change | ||||
| L0s, L1, L2, Hot Reset, Link Disable and Loopback States | X | |||
| Modified TS1 / TS2s and Alternate Protocol Negotiation | X | |||
| Interrupt Support | ||||
| Legacy Interrupt Handling | ||||
| MSI Interrupts | X | |||
| 32-bit MSI Data | X | |||
| MSI-X Interrupts | X | |||
| Error Detection and Handling | ||||
| Correctable, Non-Fatal and Fatal Errors | X | X | ||
| Advisory Non-Fatal Errors | X | X | ||
| Error Subclass field for Correctable Error Messages | ||||
| Advanced Error Reporting (AER) | X | X | ||
| Power Management | ||||
| Device Power States | X | |||
| Link Power States | X | |||
| L1 Substates | X | |||
| Active State Power Management (ASPM) - hardware controlled | X | |||
| Software Controlled Power Management | X | |||
| Power Management Events (PME, Beacon and #WAKE) | X | |||
| Dynamic Power Allocation (DPA) | ||||
| Optimized Buffer Flush Fill (OBFF) | ||||
| Latency Tolerance Reporting (LTR) | X | |||
| System Resets | ||||
| Conventional Reset Mechanisms: Cold, Warm and Hot Reset | X | X | ||
| Function Level Reset (FLR) | X | X | ||
| 1b/1b Physical Layer (64GT/s and 128GT/s) | ||||
| PAM4 | X | X | ||
| Precoding, Gray Coding and Forward Error Correction (FEC) | X | X | ||
| LTSSM Updates (TS0s, Tx EQ changes, entering Flit Mode, etc.) | X | X | ||
| Flit Mode | ||||
| Flit Format | X | X | ||
| Error Correction and Flit Retry (Standard vs Selective) | X | X | ||
| DLP Bytes in Flit and Flit Types | X | X | ||
| Flow Control (Dedicated vs Shared) | X | X | ||
| TLP Structure (Header Base, OHC, TLP Trailer, etc.) | X | X | ||
| Segments | X | X | ||
| L0p | X | X | ||
| Miscellaneous PCIe Features | ||||
| Retimers (introduced in 4.0) | overview | refresher | overview | |
| Lane Margining (introduced in 4.0) | overview | |||
| Flattening Portal Bridge (FPB) (introduced in 4.0) | overview | |||
| Hierarchy ID Reporting (introduced in 4.0) | ||||
| Designated Vendor-Specific Extended Capability (DVSEC) (introduced in 4.0) | ||||
| Enhanced Allocation (introduced in 4.0) | ||||
| Emergency Power Reduction State (introduced in 4.0) | ||||
| System Firmware Intermediary Support (introduced in 5.0) | overview | |||
| Unordered IO (UIO) (introduced in 6.1) | overview | overview | ||
| PCIe Management Interface (PCIe-MI) (introduced in 6.4) | overview | overview | ||
| Hot Plug | ||||
| Power Budgeting | ||||
| Multi-Casting | ||||
| Protocol Multiplexing (PMUX) | ||||
| Resizable BARs | ||||
| Downstream Port Containment (DPC) and Enhanced DPC (eDPC) | ||||
| Lightweight Notification (can be used for lightweight cache coherency) | ||||
| Process Address Space ID (PASID) | ||||
| Precision Time Measurement (PTM) | ||||
| Device Readiness Status (DRS) and Function Readiness Status (FRS) | ||||
Training Materials
- PDF of course slides
- "PCI Express Technology" eBook (covers PCIe 3.0)
- Fundamentals of PCI Express eLearning course (needed for pre-work before class)
- Optional add-on: PCI Express 5.0 eLearning course (discounted pricing applies)
- Optional add-on: PCIe6 Update eLearning course (discounted pricing applies)
Prerequisites
None
Related Courses
| Course Name | Classroom | Virtual Classroom | eLearning | |
| PCIe 7.0 | 5 days | 10 half-days | Show Me | |
| PCIe 6.x / 7.0 Update | 4 days | 8 half-days | Show Me | |
| PCIe 5.0 | 5 days | 10 half-days | Show Me | |
| Fundamentals of PCI Express | 1 day | 2 half-days | Show Me | |
| IO Virtualization for ARM Platforms | 4 days | 8 half-days | ||
| IO Virtualization for Intel Platforms | 4 days | 8 half-days | Show Me | |
| PCIe Security | 3 days | 6 half-days | Show Me | |
| PIPE 6.0 - PHY Interface for PCI Express and more | 1 day | 2 half-days | Show Me |
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