Compute Express Link (CXL) 3.0 - 10-Half-Day Course
Compute Express Link (CXL) 3.0 - 10-Half-Day Course

Location: Virtual-Classroom

Instructor: Ravi Budruk

Duration: 10 half-days

Date: 03/29/27 to 04/02/27

and: 04/05/27 to 04/09/27

Time: 1pm-4:30pm US Pacific Time Daily

$3495.00

Price per Learner (volume discounts available for 5 or more learners; contact us for more details)

Overview

Compute Express Link (CXL) is a high-bandwidth, low-latency serial bus interconnect between host processors and devices such as accelerators, memory controllers/buffers, and I/O devices. CXL 3.0 is based on PCI Express (PCIe) 6.0 physical layer running at 64 GT/s with x16, x8 and x4 link widths. Degraded modes run at 32 GT/s, 16 GT/s and 8 GT/s with x2 and x1 link widths.

 

CXL interconnect adds coherency and memory semantics, thus allowing for its application in heterogeneous processing systems with a variety of host processors, memory subsystems and peripheral devices interconnected. CXL has applications in standard computer systems, Artificial Intelligence (AI), Machine Learning, communication systems, and High-Performance Computing (HPC). Emerging applications require a diverse mix of CPUs, GPUs, FPGAs, peripherals such as smart NICs, and other accelerators interconnected via an open industry standard protocol with the necessary features which CXL provides. CXL provides a rich set of three protocols that include 1) CXL.io based on PCIe TLP based transactions, 2) CXL.cache and 3) CXL.mem semantics. CXL uses the PCIe stack offering full interoperability with PCIe. CXL.cachemem protocols allow for coherent transactions in memory space. These transactions employ Flit-based packet routing on the Link.

 

MindShare’s comprehensive CXL 3.0 Architecture course provides a solid foundation of platform architectures and use cases of the three CXL protocols with Type 1, Type 2 and Type 3 devices in platform example. The course details the role of the Transaction Layer protocol, Link Layer including Flit packing and unpacking, ARB/MUX and Flex Bus Logical and Electrical Physical Layer of a CXL port design. We explain enumeration and configuration process during system bring-up with details of configuration and component registers. Other topics include switch architecture, reset, manageability, RAS features, power management, performance considerations and compliance testing. The course describes new features added to the CXL 3.0 spec such as 256B and Port Based Routing (PBR) Flits, CXL.mem Back-Invalidation, Dynamic Capacity Devices (DCD), LD-FAM and G-FAM Devices, Global Integrated Memory (GIM), Multi-Headed (MH) Devices, Hierarchy Based Routing (HBR) and Port Based Routing (PBR), Direct Peer-to-Peer Routing and lots more.

Course Outline

  • CXL Features and Architecture Overview
    • CXL 1.1, CXL 2.0 and CXL 3.0 Features
    • CXL.mem, CXL.cache and CXL.io
    • Type 1 (with cache), Type 2 (with cache and memory, Type 3 (with memory) Devices
    • Switch and MLD device architecture overview
    • CXL 3.0 features overview
    • Layered architecture overview
    • Transaction flows in platforms with PCIe, CXL Type 1, 2, 3 Devices
    • Cache coherency and MESI protocol tutorial
  • Transaction Layer
    • CXL.mem protocol
    • CXL.cache protocol
    • CXL.mem back-invalidation and CXL.cache device scaling
    • CXL.io protocol PTH and UIO Ordering Rules
  • Link Layer
    • IO Flit Packing
    • Cache/Mem Flit Packing
    • Control Flits
    • 68B Flits 256B and PBR Flits
    • Cachemem Link Layer Retry (LLR) mechanism
    • Flow Control
    • Viral Feature
  • ARB/Mux Layer
    • Arbitration and Flit Multiplexing/DeMuxing
    • vLSM and Link Power Management
    • ALMP Flits
  • Physical Layer
    • Protocol ID
    • Flit Header
    • NOP Flits, IDLE Flits, Latency Optimized Flits
    • CRC, FEC
    • Synch Header Bypass
    • 1b/1b encoding 
    • Link Training
  • Reset
    • Cold reset
    • Warm reset
    • Hot reset
    • CXL reset
    • Function Level reset (FLR)
  • Power Management
    • Runtime control PM
    • Physical Layer PM
    • CXL.io PM
    • CXL.cachemem PM
  • RAS and Error Handling
    • EFN Message
    • Viral Handling
    • Error Logging
  • Enumeration and Manageability
    • Enumeration in 1.1 and 2.0 Platforms
    • Memory Interleaving Memory Interleaving in CXL 3.0
  • Control and Status Registers
    • Configuration registers and DVSEC Component Registers
    • Backwards compatibiity to CXL 1.1
    • CXL 3.0 registers

Training Materials

Prerequisites

Complete working knowledge of PCI Express architecture. Computer architecture fundamentals. Cache coherency concepts incuding MESI protocol